ARM PrimeCell PL241 Technical Reference Manual Download Page 65

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Programmer’s Model

ARM DDI 0389B

3-5

smc_set_cycles

0x1014

N/A

See

SMC Set Cycles Register at 0x1014

page 3-11.

smc_set_opmode

0x1018

N/A

See

SMC Set Opmode Register at 0x1018

page 3-12.

smc_refresh_period_0

0x1020

R/W

0x00000000

See

SMC Refresh Period 0 Register at 0x1020

on page 3-15.

smc_sram_cycles0_<0-3>

0x1000

+ chip

configuration
base address

0x0002B3CC

smc_sram_cycles configuration where:

See

SMC SRAM Cycles Registers <0-3> at

0x1100, 0x1120, 0x1140, 0x1160

on page 3-15.

smc_opmode0_<0-3>

chip

configuration
base address

0x00000802

opmode configuration where:

See

SMC Opmode Registers <0-3> at 0x1104,

0x1124, 0x1144, 0x1164

on page 3-16.

smc_user_status

0x1200

0x00000000

See

SMC User Status Register at 0x1200

page 3-18.

smc_user_config

0x1204

See

SMC User Configuration Register at

0x1204

on page 3-19.

smc_int_cfg

0x1E00

R/W

0x00000000

See

SMC Integration Configuration Register at

0x1E00

on page 4-2.

smc_int_inputs

0x1E04

See

Integration Inputs Register at 0x1E04

page 4-3.

smc_int_outputs

0x1E08

See

Integration Outputs Register at 0x1E08

page 4-4.

smc_periph_id_<0-3>

0x1FE0-0x1FEC

See registers

smc_periph_id_n

See

SMC Peripheral Identification Registers

<0-3> at 0x1FE0-0x1FEC

on page 3-19.

smc_pcell_id_<0-3>

0x1FF0-0x1FFC

See registers

smc_pcell_id_n

See

SMC PrimeCell Identification Registers

<0-3> at 0x1FF0-0x1FFC

on page 3-22.

Table 3-1 Register summary (continued)

Name

Base offset

Type

Reset value

Description

Summary of Contents for PrimeCell PL241

Page 2: ...ntained in this document are given by ARM Limited in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document...

Page 3: ...ut this manual x Feedback xiv Chapter 1 Introduction 1 1 About the AHB MC 1 2 1 2 Supported devices 1 5 Chapter 2 Functional Overview 2 1 Functional description 2 2 2 2 SMC 2 4 2 3 Functional operation 2 7 2 4 SMC functional operation 2 15 Chapter 3 Programmer s Model 3 1 About the programmer s model 3 2 3 2 Register summary 3 3 3 3 Register descriptions 3 6 ...

Page 4: ...sters 4 2 Chapter 5 Device Driver Requirements 5 1 Memory initialization 5 2 Appendix A Signal Descriptions A 1 About the signals list A 2 A 2 Clocks and resets A 3 A 3 AHB signals A 4 A 4 SMC memory interface signals A 5 A 5 SMC miscellaneous signals A 6 A 6 Low power interface A 7 A 7 Configuration signal A 8 A 8 Scan chains A 9 Glossary ...

Page 5: ...Table 2 9 Asynchronous write in multiplexed mode SRAM cycles register settings 2 31 Table 2 10 Page read opmode chip register settings 2 31 Table 2 11 Page read SRAM cycles register settings 2 31 Table 2 12 Synchronous burst read opmode chip register settings 2 32 Table 2 13 Synchronous burst read SRAM cycles register settings 2 32 Table 2 14 Synchronous burst read in multiplexed mode opmode chip ...

Page 6: ...gister bit assignments 3 19 Table 3 14 smc_periph_id Register bit assignments 3 19 Table 3 15 smc_periph_id_0 Register bit assignments 3 20 Table 3 16 smc_periph_id_1 Register bit assignments 3 21 Table 3 17 smc_periph_id_2 Register bit assignments 3 21 Table 3 18 smc_periph_id_3 Register bit assignments 3 21 Table 3 19 smc_pcell_id Register bit assignments 3 22 Table 3 20 smc_pcell_id_0 Register ...

Page 7: ...gure 2 5 Big endian implementation 2 10 Figure 2 6 AHBC memory map 2 11 Figure 2 7 Request to enter low power mode 2 13 Figure 2 8 AHB domain denying a low power request 2 13 Figure 2 9 Accepting requests 2 14 Figure 2 10 SMC aclk domain FSM 2 15 Figure 2 11 Chip configuration registers 2 23 Figure 2 12 Device pin mechanism 2 25 Figure 2 13 Software mechanism 2 26 Figure 2 14 Asynchronous read 2 2...

Page 8: ... 3 10 smc_direct_cmd Register bit assignments 3 10 Figure 3 11 smc_set_cycles Register bit assignments 3 11 Figure 3 12 smc_set_opmode Register bit assignments 3 12 Figure 3 13 smc_refresh_period_0 Register bit assignments 3 15 Figure 3 14 smc_sram_cycles Register bit assignments 3 15 Figure 3 15 smc_opmode Register bit assignments 3 16 Figure 3 16 smc_user_status Register bit assignments 3 18 Fig...

Page 9: ...ARM Limited All rights reserved ix Preface This preface introduces the PrimeCell AHB SRAM NOR Memory Controller MC PL241 Technical Reference Manual It contains the following sections About this manual on page x Feedback on page xiv ...

Page 10: ...n Chip SoC device that uses the AHB MC The manual describes the external functionality of the AHB MC Using this manual This manual is organized into the following chapters Chapter 1 Introduction Read this chapter for a high level view of the AHB MC and a description of its features Chapter 2 Functional Overview Read this chapter for a description of the major components of the AHB MC and how they ...

Page 11: ...ents such as menu names Denotes signal names Also used for terms in descriptive lists where appropriate monospace Denotes text that you can enter at the keyboard such as commands file and program names and source code monospace Denotes a permitted abbreviation for a command or option You can enter the underlined text instead of the full command or option name monospace italic Denotes arguments to ...

Page 12: ...fined so the bus or signal can assume any value within the shaded area at that time The actual level is unimportant and does not affect normal operation Key to timing diagram conventions Signals The signal conventions are Signal level The level of an asserted signal depends on whether the signal is active HIGH or active LOW Asserted means HIGH for active HIGH signals and LOW for active LOW signals...

Page 13: ... wide decimal value of 9 8 h3F is an eight bit wide hexadecimal value of 0x3F This is equivalent to b00111111 8 b1111 is an eight bit wide binary value of b00001111 Further reading This section lists publications by ARM Limited and by third parties ARM Limited periodically provides updates and corrections to its documentation See http www arm com for current errata sheets addenda and the Frequentl...

Page 14: ...gestions about this product contact your supplier giving the product name a concise explanation of your comments Feedback on this manual If you have any comments on this manual send email to errata arm com giving the title the number the relevant page number s to which your comments apply a concise explanation of your comments ARM Limited also welcomes general suggestions for additions and improve...

Page 15: ... 0389B Copyright 2006 ARM Limited All rights reserved 1 1 Chapter 1 Introduction This chapter introduces the AHB MC It contains the following sections About the AHB MC on page 1 2 Supported devices on page 1 5 ...

Page 16: ...h access to the external memory The AHB port has a bridge interface to the memory controller There is a separate AHB port to configure the memory controller Specific configurations of the SMC are instantiated to target specific memory devices Figure 1 1 shows the AHB MC PL241 configuration Figure 1 1 AHB MC PL241 configuration This section describes AHB interface on page 1 3 AHB to APB bridge on p...

Page 17: ...e RAW hazard detection buffer avoids RAW hazards AHB response signals are registered to improve timing locked transfers are supported within a 512MB region HWDATA is registered to improve internal timing paths a big endian 32 bit mode option is implemented AHB error response logic is removed as no internal components generate errors This interface is a fully validated component This ensures that i...

Page 18: ...2 bit programmable cycle timings and memory width per chip select atomic switching of memory device and controller operating modes support for the PL220 External Bus Interface EBI PrimeCell enabling sharing of external address and data bus pins between memory controller interfaces support for a low power interface support for a remap signal support for clock domains to be synchronous or asynchrono...

Page 19: ...ot support these non array accesses Therefore W18 devices can only carry out non array operations such as Read Status in asynchronous modes of operation Cellular RAM 1 0 64MB PSRAM for example mt45w4mw16bfb_701_1us You can program these devices using a CRE pin or by software access Whenever you program these devices through software access using a sequence of two reads followed by two writes ensur...

Page 21: ... Chapter 2 Functional Overview This chapter describes the major components of the AHB MC and how they operate It contains the following sections Functional description on page 2 2 SMC on page 2 4 Functional operation on page 2 7 SMC functional operation on page 2 15 ...

Page 22: ... internal interconnect some optimizations are made in the interface to improve performance See AHB interface operation on page 2 7 for more information 2 1 2 AHB to APB bridge The internal memory controllers of the AHB MC use the AMBA3 APB protocol for their configuration ports To enable the AHB MC to externally function as an AHB device the APB configuration ports are connected to an AHB to APB b...

Page 23: ...s for clocking the different domains See Clock domain operation on page 2 11 for more information 2 1 4 Low power interface The memory controller has two low power interfaces one for each clock domain These operate with a simple three signal protocol It is expected that a system clock controller drives these interfaces and associated clocks Each domain has individual control to enable independent ...

Page 24: ...blocks of the SMC are SMC interface on page 2 5 APB slave interface on page 2 5 Format on page 2 5 Memory manager on page 2 5 Memory interface on page 2 5 Pad interface on page 2 6 Interrupts on page 2 6 3 VODYH LQWHUIDFH 0HPRU PDQDJHU RUPDW 60 LQWHUIDFH RZ SRZHU LQWHUIDFH 0HPRU LQWHUIDFH 3DG LQWHUIDFH LQWHUIDFH 65 0 PHPRU LQWHUIDFH FORFN GRPDLQ 0HPRU FORFN GRPDLQ QWHUUXSWV ...

Page 25: ... also maps AHB memory transfers onto appropriate memory transfers and passes these to the memory interface through the command FIFO See Format block on page 2 19 for more information 2 2 4 Memory manager The memory manager tracks and controls the current state of smc_aclk domain logic The block is responsible for updating timing registers and controlling direct commands issued to memory controllin...

Page 26: ...nals Clock and reset signals are omitted Figure 2 4 SMC SRAM pad interface external connections 2 2 7 Interrupts The SRAM memory interface support interrupts The interrupt is triggered on the rising edge of the smc_int_0 input for the SRAM memory interface See Interrupts operation on page 2 27 for more information 65 0 SDG LQWHUIDFH VPFBGDWDBLQB VPFBZDLWB VPFBLQWB VPFBFONBRXWB VPFBFVBQB VPFBZHBQB ...

Page 27: ...e on page 2 10 Removal of AHB error response logic on page 2 10 AHB fixed burst types All AHB fixed length bursts directly map to burst types that the internal interconnect uses The internal interconnect and the memory controller are based on transferring bursts of data The larger the burst size the more efficient the transfer and overall performance The standard AHB fixed length burst types are d...

Page 28: ...masters then the AHB system arbitration can break a burst Also because the bridge converts INCR to INCR4 broken INCR4s occur when undefined length INCRs of a length not equal to a multiple of four are performed To support broken bursts the bridge must keep track of how many beats of a burst have been performed and ensure it obeys the protocol of the interconnect For read bursts this means draining...

Page 29: ...efore the write This means that the data read might be the value before the most recent write The bridge has to detect these potential cases and stall the read transfer until any buffered writes that might cause a RAW hazard have been completed The bridge contains logic to monitor up to four outstanding write addresses If an incoming read occurs to a 4KB region that has been written to then it is ...

Page 30: ...at if the tie off is asserted then the data buses are reordered Figure 2 5 Big endian implementation Removal of AHB error response logic The internal protocol used within AHB MC supports the concept of errors However none of the components used ever generate errors This means that the bridge does not require any logic to generate AHB errors because there are no circumstances when errors can be gen...

Page 31: ...es the AHB interfaces and bus matrix The static memory controller has a separate clock input in this domain This is called smc_aclk This signal is separated to enable the clock to be stopped independently of hclk for low power operation see Low power interface operation on page 2 12 These two clocks must always be driven from the same clock source The input signal hresetn resets this clock domain ...

Page 32: ...B clock domain static memory clock domain Each domain uses a simple three signal interface to indicate whether the clocks are required The signals consist of a request input domain _csyreq an acknowledge output domain _csysack Table 2 1 Static memory clocking options Options Tie off values Fully synchronous hclk smc_mclk0 smc_async0 smc_msync0 1 smc_a_gt_m0_sync 0 Synchronous multiples hclk n x sm...

Page 33: ...active signal is used to indicate whether the request has been accepted or denied If the request is accepted domain _cactive is LOW as shown in Figure 2 7 If the request is denied domain _cactive is HIGH If the request is accepted then the clock to that domain can be switched off The peripheral is brought out of low power state by restarting the clock and driving domain _csysreq HIGH as shown at T...

Page 34: ...T1 When the memory controller is happy for the clock to be switched off the smc_csysack signal is driven LOW to acknowledge the request as shown at T2 smc_cactive is driven LOW so the system clock controller knows the request has been accepted When acknowledged the system clock controller can disable both the smc_aclk and smc_mclk0 signals The two domains have separate interfaces to enable individ...

Page 35: ...he operation of the SMC is based on three operating states In this section each state is described Figure 2 10 shows the state machine Figure 2 10 SMC aclk domain FSM The SMC states are as follows Reset Power is applied to the device and hresetn is held LOW Ready Normal operation of the device You can access the SMC register bank through the AHB configuration port and external memory devices acces...

Page 36: ...APB smc_memc_cfg_set Register the SMC receives a low power request through the SMC low power interface Low power to Ready The SMC exits the Low power state back to Ready when either the SMC low power request bit is cleared in the APB smc_memc_cfg_clr Register the SMC low power interface negates the low power request Low power to Reset When Reset is asserted to the smc_aclk reset domain it enters t...

Page 37: ...ecause of the integer relationship of the clocks you might not be able to get the maximum performance from the system because of constraints placed on the bus frequency by the external memory clock speed In synchronous mode the handshaking between the smc_aclk and smc_mclk0 domains enables synchronous operation of the two clocks at multiples of each other that is ratios of n 1 and 1 m Asynchronous...

Page 38: ...eral purpose input ports that are readable from the APB interface through the smc_user_status Register If you do not require these ports then tie them either HIGH or LOW These ports are connected directly to the APB interface block Therefore if they are driven from external logic that is not clocked by the SMC smc_aclk signal then you require external synchronization registers See also the SMC Use...

Page 39: ...ed interface to the external infrastructure the APB interface always adds a wait state for all reads and writes by driving pready LOW during the first cycle of the access phase In two instances a delay of more than one wait state can be generated when a direct command is received and there are outstanding commands that prevent a new command being stored in the command FIFO when an APB access is re...

Page 40: ...d to the memory device the AHB address is aligned to the memory width This is done because the AHB address is a byte aligned address while the memory address is a memory width aligned address Note During initial configuration of a memory device the memory mode register can be accessed with a sequence of transfers to specific addresses You must take into consideration the shifting performance by th...

Page 41: ...f the read and write data FIFOs and the programmed memory burst must not exceed this upper limit For read transfers the maximum memory burst length is the depth of the read data FIFO and it is four For writes the burst length is the depth of the write FIFO and is four Booting using the SRAM The SMC enables the lowest SRAM chip select normally chip 0 to be bootable To enable SRAM memory to be boota...

Page 42: ... all FIFOs are empty all memory interface blocks are IDLE When the Low power state is entered no new memory transfers are accepted until the SMC has been moved out of Low power state The SMC does not request to move out of Low power state and never refuses a power down request Chip configuration registers The SMC provides a mechanism for synchronizing the switching of operating modes of the SMC wi...

Page 43: ...ster update is taking place the smc_direct_cmd Register indicates either a modereg operation or an memory access has taken place and is complete The chip configuration registers are available as read only registers in the address map of the APB interface Figure 2 11 Chip configuration registers PHPFBFIJ FKLS BFIJ FKLS BFIJ FKLS BFIJ FKLS BFIJ DSEBLI PDQDJHU 4 VHW F FOHV VHW RSPRGH 4 FKLS F FOHV FK...

Page 44: ...ating the controller and memory configuration registers Device pin mechanism For memories that use an input pin to indicate that a write is intended for the configuration register for example in some PSRAM devices the write mechanism can be done through the APB direct command register Figure 2 12 on page 2 25 shows the sequence of events Software mechanism For memories that require a sequence of r...

Page 45: ... LQWHUIDFH DQG VHWV D UHTXHVW UHT VLJQDO 7KH PHPRU FRQWUROOHU GRHV QRW DFFHSW DQ PRUH FRQILJXUDWLRQ SRUW FRPPDQGV XQWLO UHT LV FOHDUHG KHQ WKH PHPRU LQWHUIDFH LVVXHV WKH PRGH UHT FRPPDQG WR PHPRU LW UHVSRQGV WR WKH UHT VLJQDO ZLWK DQ DFN UHVSRQVH VLJQDO 7KH PHPRU LQWHUIDFH EORFNV DQ PRUH DFFHVVHV WR WKDW FKLS VHOHFW XQWLO UHT LV FOHDUHG 7KH PHPRU FRQWUROOHU GHWHFWV WKH DFN VLJQDO DQG XSGDWHV WKH P...

Page 46: ...RQWUROOHU GRHV QRW DFFHSW DQ PRUH FRQILJXUDWLRQ SRUW FRPPDQGV XQWLO UHT LV FOHDUHG KHQ WKH PHPRU LQWHUIDFH GHWHFWV WKH UHT VLJQDO LW WULHV WR PDWFK DOO FRPPDQGV LVVXHG WR WKH UHTXLUHG FKLS VHOHFW ZLWK WKH PDWFK YDOXH KHQ WKH PHPRU LQWHUIDFH PDWFKHV WKH UHTXLUHG FKLS VHOHFW DQG PDWFK YDOXH WR WKH GDWD EXV XVLQJ E WH ODQH VWUREHV WR GHWHUPLQH YDOLGLW LW DVVHUWV DFN DQG EORFNV DQ PRUH DFFHVVHV WR WKD...

Page 47: ...nally a read command is not issued unless there is space for all the impending data in the read data FIFO Note You must not set the rd_bl parameter in the smc_opmode Register to a value greater than the read data FIFO depth of four If enabled the EBI can prevent commands being issued when the SMC is not granted the external bus Figure 2 14 on page 2 29 to Figure 2 23 on page 2 38 show the timing p...

Page 48: ...age 2 31 Asynchronous page mode read on page 2 31 Synchronous burst read on page 2 32 Synchronous burst read in multiplexed mode on page 2 34 Synchronous burst write on page 2 35 Synchronous burst write in multiplexed mode on page 2 36 Synchronous read and asynchronous write on page 2 37 Asynchronous read Table 2 2 and Table 2 3 list the smc_opmode0_ 0 3 and SRAM Register settings See Register sum...

Page 49: ...de with tRC 7 and tCEOE 5 Figure 2 15 Asynchronous read in multiplexed mode VPFBPFON VPFBFVBQB VPFBRHBQB VPFBDGGB VPFBGDWDBLQB UHDGBGDWD W5 W 2 Table 2 4 Asynchronous read in multiplexed mode opmode chip register settings Field mw rd_sync rd_bl wr_sync wr_bl baa adv bls ba Value b0 b000 b1 Table 2 5 Asynchronous read in multiplexed mode SRAM cycles register settings Field t_rc t_wc t_ceoe t_wp t_p...

Page 50: ...meter tWC is controlling the deassertion of smc_we_n_0 You can use it to vary the hold time of smc_cs_n_0 3 0 smc_add_0 31 0 and smc_data_out_0 31 0 This differs from the read case where the timing parameter tCEOE controls the delay in the assertion of smc_oe_n_0 Additionally smc_we_n_0 is always asserted one cycle after smc_cs_n_0 3 0 to ensure the address bus is valid Figure 2 16 Asynchronous wr...

Page 51: ...and Table 2 11 list the smc_opmode0_ 0 3 and SRAM Register settings Table 2 8 Asynchronous write in multiplexed mode opmode chip register settings Field mw rd_sync rd_bl wr_sync wr_bl baa adv bls ba Value b0 b000 b0 b0 Table 2 9 Asynchronous write in multiplexed mode SRAM cycles register settings Field t_rc t_wc t_ceoe t_wp t_pc t_tr Value b0111 b100 VPFBPFON VPFBFVBQB VPFBDGYBQB VPFBGDWDBHQB VPFB...

Page 52: ...onous reads and the burst length to the page size Note Multiplexed mode page accesses are not supported Figure 2 18 Page read Synchronous burst read Table 2 12 and Table 2 13 list the smc_opmode0_ 0 3 and SRAM Register settings VPFBFVBQB VPFBRHBQB VPFBDGGB VPFBGDWDBLQB UHDGBGDWD VPFBPFON W5 W3 W3 W 2 Table 2 12 Synchronous burst read opmode chip register settings Field mw rd_sync rd_bl wr_sync wr_...

Page 53: ...his enables the easiest timing closure Additionally you must configure the memory for smc_wait_0 to be active LOW In synchronous operation the SMC relies on the smc_wait_0 signal being deasserted HIGH to indicate that the memory can finish the transfer When in synchronous mode some memories do not deassert the smc_wait_0 signal during non array read transfers Non array read transfers are typically...

Page 54: ...n multiplexed mode Figure 2 20 Synchronous burst read in multiplexed mode Table 2 14 Synchronous burst read in multiplexed mode opmode chip register settings Field mw rd_sync rd_bl wr_sync wr_bl baa adv bls ba Value b1 burst length Table 2 15 Synchronous burst read in multiplexed mode read SRAM cycles register settings Field t_rc t_wc t_ceoe t_wp t_pc t_tr Value b0100 b010 VPFBFVBQB VPFBDGYB VPFBR...

Page 55: ...ait_0 signal is again registered with the fed back clock and smc_mclk0 before being used The smc_wait_0 signal is used in the smc_mclk0 domain to the memory interface FSM Figure 2 21 Synchronous burst write Table 2 16 Synchronous burst write opmode chip register settings Field mw rd_sync rd_bl wr_sync wr_bl baa adv bls ba Value b1 burst length b1 Table 2 17 Synchronous burst write SRAM cycles regi...

Page 56: ...ltiplexed mode Figure 2 22 Synchronous burst write in multiplexed mode Table 2 18 Synchronous burst write in multiplexed mode opmode chip register settings Field mw rd_sync rd_bl wr_sync wr_bl baa adv bls ba Value b1 burst length b1 Table 2 19 Synchronous burst write in multiplexed mode SRAM cycles register settings Field t_rc t_wc t_ceoe t_wp t_pc t_tr Value b0100 b001 VPFBFVBQB VPFBDGYBQB VPFBZH...

Page 57: ...us read and asynchronous write The turnaround time is enforced between Reads followed by writes Writes followed by reads Read following a read from a different chip select Table 2 20 Synchronous read and asynchronous write opmode chip register settings Field mw rd_sync rd_bl wr_sync wr_bl baa adv bls ba Value b1 b001 b0 b000 b0 b1 b0 Table 2 21 Synchronous read and asynchronous write opmode chip r...

Page 58: ... be the number of clock cycles required before valid data is available following the assertion of cs_n when using memory devices that are wait enabled you must program tRC to be the number of clock cycles required before wait is active and stable following the assertion of cs_n That is t_RC 3 t_CEOE Note t_CEOE is only required if wait is asserted when oe_n goes LOW VPFBPFON VPFBFONBRXWB VPFBIEFON...

Page 59: ...written following the assertion of cs_n when using memory devices that are wait enabled you must program tWC to be the number of clock cycles required before wait is active and stable following the assertion of cs_n That is t_WC 3 Note If a memory device is configured so that there are two or less clock cycles between the assertion of wait and data being required then you must program tWC as if th...

Page 61: ...Chapter 3 Programmer s Model This chapter describes the registers of the SMC and provides information for programming the device It contains the following sections About the programmer s model on page 3 2 Register summary on page 3 3 Register descriptions on page 3 6 ...

Page 62: ...ol of operating state of the SMC SMC chip select configuration registers These registers hold the operating parameters of each chip select SMC user configuration registers These registers provide general purpose I O for user specific applications SMC integration test registers Use these registers to verify correct integration of the SMC within a system by enabling non AMBA ports to be set and read...

Page 63: ... shows the SMC chip 0 3 configuration register map Figure 3 3 SMC chip configuration register map VPFBVHWBRSPRGH VPFBVHWBF FOHV VPFBGLUHFWBFPG VPFBPHPFBFIJBFOU VPFBPHPLIBFIJ VPFBPHPFBVWDWXV VPFBPHPFBFIJBVHW VPFBUHIUHVKBSHULRGB RSPRGH VUDPBF FOHV 65 0 FKLS FRQILJXUDWLRQ KLS VPFBRSPRGH B VPFBVUDPBF FOHV B VPFBRSPRGH B VPFBVUDPBF FOHV B VPFBRSPRGH B VPFBVUDPBF FOHV B VPFBRSPRGH B VPFBVUDPBF FOHV B KL...

Page 64: ...ster map Table 3 1 lists the SMC Registers VPFBXVHUBFRQILJ VPFBXVHUBVWDWXV VPFBSFHOOBLGB VPFBSFHOOBLGB VPFBSFHOOBLGB VPFBSFHOOBLGB VPFBSHULSKBLGB VPFBSHULSKBLGB VPFBSHULSKBLGB VPFBSHULSKBLGB Table 3 1 Register summary Name Base offset Type Reset value Description smc_memc_status 0x1000 RO 0x00000000 See SMC Memory Controller Status Register at 0x1000 on page 3 6 smc_memif_cfg 0x1004 RO 0x0000002D ...

Page 65: ...ers 0 3 at 0x1104 0x1124 0x1144 0x1164 on page 3 16 smc_user_status 0x1200 RO 0x00000000 See SMC User Status Register at 0x1200 on page 3 18 smc_user_config 0x1204 WO See SMC User Configuration Register at 0x1204 on page 3 19 smc_int_cfg 0x1E00 R W 0x00000000 See SMC Integration Configuration Register at 0x1E00 on page 4 2 smc_int_inputs 0x1E04 RO See Integration Inputs Register at 0x1E04 on page ...

Page 66: ...ster bit assignments Figure 3 6 smc_memc_status Register bit assignments Table 3 2 lists the register bit assignments VWDWH LQWBHQ UDZBLQWBVWDWXV LQWBVWDWXV 8QGHILQHG 5HVHUYHG 5HVHUYHG Table 3 2 smc_memc_status Register bit assignments Bits Name Function 31 6 Reserved read undefined 5 raw_int_status0 Current raw interrupt status for interface 0 4 Reserved read undefined 3 int_status0 Current inter...

Page 67: ...ists the register bit assignments PHPRU BW SH PHPRU BFKLSV PHPRU BZLGWK UHPDS H FOXVLYHBPRQLWRUV 8QGHILQHG 5HVHUYHG Table 3 3 smc_memif_cfg Register bit assignments Bits Name Function 31 18 Reserved read undefined 17 16 exclusive_monitors Returns the number of exclusive access monitor resources that are implemented in the SMC b00 0 monitors b01 1 monitors b10 2 monitors b11 4 monitors 15 7 Reserve...

Page 68: ...en to in the Reset state Figure 3 8 shows the register bit assignments Figure 3 8 smc_memc_cfg_set Register bit assignments 3 2 memory_chips0 Returns the number of different chip selects that the memory interface 0 supports b00 1 chip b01 2 chips b10 3 chips b11 4 chips 1 0 memory_type0 Returns the memory interface 0 type b00 reserved b01 SRAM b10 NAND b11 reserved Table 3 3 smc_memif_cfg Register...

Page 69: ... 5 lists the register bit assignments Table 3 4 smc_memc_cfg_set Register bit assignments Bits Name Function 31 3 Reserved undefined Write as zero 2 low_power_req b0 no effect b1 request the SMC to enter Low power state when it next becomes idle 1 Reserved undefined Write as zero 0 int_enable0 b0 no effect b1 interrupt enable memory interface 0 LQWBGLVDEOH 5HVHUYHG ORZBSRZHUBH LW 8QGHILQHG Table 3...

Page 70: ...egister bit assignments Bits Name Function 31 26 Reserved undefined Write as zero 25 23 chip_select Selects chip configuration register bank to update and enables chip mode register access depending on cmd_type The encoding is b000 b011 chip selects 1 4 on interface 0 b100 b111 reserved 22 21 cmd_type Determines the current command The encoding is b00 UpdateRegs and AHB command b01 ModeReg access ...

Page 71: ...er bit assignments Table 3 7 lists the register bit assignments 6HWBW 6HWBW 6HWBW 6HWBW 6HWBW 6HWBW 6HWBW 8QGHILQHG Table 3 7 smc_set_cycles Register bit assignments Bits Name Function 31 23 Reserved undefined Write as zero 22 20 Set_t6 Reserved 19 17 Set_t5 Holding register for value to be written to the specific chip Register tTR field 16 14 Set_t4 Holding register for value to be written to the...

Page 72: ...rite only smc_set_opmode Register cannot be written to in either the Reset or Low power state Figure 3 12 shows the register bit assignments Note Table 3 8 on page 3 13 describes register holding see Memory manager operation on page 2 22 for more information Figure 3 12 smc_set_opmode Register bit assignments VHWBPZ VHWBUGBV QF VHWBUGBEO VHWBZUBV QF VHWBZUBEO 8QGHILQHG VHWBEOV VHWBDGY VHWBEDD VHWB...

Page 73: ... boundary when set_rd_sync 0 the AHB MC always aligns write bursts to the memory burst boundary when set_wr_sync 0 12 set_bls Holding register for value to be written to the specific SRAM chip smc_opmode Register byte lane strobe bls field This bit affects the assertion of the byte lane strobe outputs b0 bls timing equals chip select timing This is the default setting b1 bls timing equals smc_we_n...

Page 74: ...for value to be written to the specific SRAM chip smc_opmode Register bls field Encodes the memory burst length b000 1 beat b001 4 beats b010 8 beats b011 16 beats b100 32 beats b101 continuous b110 b111 reserved 2 set_rd_sync Holding register before being written to the specific SRAM chip smc_opmode Register rd_sync field Memory in sync mode when set 1 0 set_mw Holding register for value to be wr...

Page 75: ... only smc_sram_cycles Register cannot be read in the Reset state Figure 3 14 shows the register bit assignments Figure 3 14 smc_sram_cycles Register bit assignments 8QGHILQHG SHULRG Table 3 9 smc_refresh_period_0 Register bit assignments Bits Name Function 31 4 Reserved read undefined 3 0 period Sets the number of consecutive memory bursts that are permitted prior to the AHB MC deasserting chip se...

Page 76: ...alue of memory width for all other chip selects is the configured width You must set all other bits to 0x0 apart from address_match and address_mask These are set by tie offs at the top level Figure 3 15 shows the register bit assignments Figure 3 15 smc_opmode Register bit assignments Table 3 10 smc_sram_cycles Register bit assignments Bits Name Function 31 20 Reserved read undefined 19 17 t_tr T...

Page 77: ... 64 beat boundary 011 burst split on 128 beat boundary 100 burst split on 256 beat boundary others reserved Note For asynchronous transfers the AHB MC always aligns read bursts to the memory burst boundary when rd_sync 0 the AHB MC always aligns write bursts to the memory burst boundary when wr_sync 0 12 bls This bit affects the assertion of the byte lane strobe outputs b0 bls timing equals chip s...

Page 78: ...6 wr_sync When set the memory operates in write sync mode 5 3 rd_bl Determines the memory burst lengths for reads b000 1 beat b001 4 beats b010 8 beats b011 16 beats b100 32 beats b101 continuous b110 b111 reserved 2 rd_sync When set the memory operates in read sync mode 1 0 mw Determines the SMC memory data bus width b00 8 bits b01 16 bits b10 32 bits b11 reserved Table 3 11 smc_opmode Register b...

Page 79: ...a single register that holds a 32 bit peripheral ID value They are read by an external master to determine what version of the device the SMC is None of the registers 0 3 can be read in the Reset state Table 3 14 lists the register bit assignments VPFBXVHUBFRQILJ 8QGHILQHG Table 3 13 smc_user_config Register bit assignments Bits Name Function 31 8 Reserved undefined Write as zero 7 0 smc_user_conf...

Page 80: ...pheral Identification Register 2 on page 3 21 SMC Peripheral Identification Register 3 on page 3 21 SMC Peripheral Identification Register 0 The smc_periph_id_0 Register is hard coded and the fields within the register indicate the value Table 3 15 lists the register bit assignments 8QGHILQHG 8QGHILQHG UHYLVLRQ UHYLVLRQ GHVLJQHUB GHVLJQHUB GHVLJQHU SDUWBQXPEHU SDUWBQXPEHUB SDUWBQXPEHUB FWXDO UHJLV...

Page 81: ...indicate the value of 0x0 Table 3 18 lists the register bit assignments Table 3 16 smc_periph_id_1 Register bit assignments Bits Name Function 31 8 Reserved read undefined 7 4 designer_0 These bits read back as 0x1 3 0 part_number_1 These bits read back as 0x3 Table 3 17 smc_periph_id_2 Register bit assignments Bits Name Function 31 8 Reserved read undefined 7 4 revision These bits read back as 0x...

Page 82: ...ure 3 19 shows the register bit assignments Figure 3 19 smc_pcell_id Register bit assignments Table 3 19 smc_pcell_id Register bit assignments SMC pcell_id_0 3 register Bits Value Register Bits Description smc_pcell_id_3 31 8 Read undefined 31 24 0xB1 smc_pcell_id_3 7 0 These bits read back as 0xB1 smc_pcell_id_2 31 8 Read undefined 23 16 0x05 smc_pcell_id_2 7 0 These bits read back as 0x05 smc_pc...

Page 83: ...r 0 The smc_pcell_id_0 Register is hard coded and the fields within the register indicate the value Table 3 20 lists the register bit assignments SMC PrimeCell Identification Register 1 The smc_pcell_id_1 Register is hard coded and the fields within the register indicate the value Table 3 21 lists the register bit assignments Table 3 20 smc_pcell_id_0 Register bit assignments Bits Name Function 31...

Page 84: ... PrimeCell Identification Register 3 The smc_pcell_id_3 Register is hard coded and the fields within the register indicate the value Table 3 23 lists the register bit assignments Table 3 22 smc_pcell_id_2 Register bit assignments Bits Name Function 31 8 Reserved read undefined 7 0 smc_pcell_id_2 These bits read back as 0x5 Table 3 23 smc_pcell_id_3 Register bit assignments Bits Name Function 31 8 ...

Page 85: ...ited All rights reserved 4 1 Chapter 4 Programmer s Model for Test This chapter describes the additional logic for functional verification and production testing It contains the following section SMC integration test registers on page 4 2 ...

Page 86: ...fg Register selects the integration test registers This register is only for test This register cannot be read or written to in the Reset state Figure 4 2 shows the register bit assignments Figure 4 2 smc_int_cfg Register bit assignments VPFBLQWBRXWSXWV VPFBLQWBLQSXWV VPFBLQWBFIJ Table 4 1 SMC test register summary Name Base offset Type Reset value Description smc_int_cfg 0x1E00 R W 0x0 SMC Integr...

Page 87: ...bit assignments Table 4 3 lists the register bit assignments Table 4 2 smc_int_cfg Register bit assignments Bits Name Function 31 1 Undefined Read undefined Write as zero 0 int_test_en When set outputs are driven from the integration test registers and tied off and inputs can change for integration testing VPFBPV QF VPFBDV QF VPFBHELEDFNRII VPFBHELJQW VPFBFV VUHT 8QGHILQHG VPFBXVHBHEL Table 4 3 sm...

Page 88: ...2 smc_ebignt0 Returns the value of the smc_ebigrant0 input 1 smc_use_ebi Returns the value of the smc_use_ebi input 0 smc_csysreq Returns value of this external input Table 4 3 smc_int_inputs Register bit assignments continued Bits Name Function VPFBHELUHT VPFBFV VDFN VPFBFDFWLYH 8QGHILQHG Table 4 4 smc_int_outputs Register bit assignments Bits Name Function 31 3 Reserved undefined write as zero 2...

Page 89: ...mited All rights reserved 5 1 Chapter 5 Device Driver Requirements This chapter contains various flow diagrams to aid in the development of a software driver for the SMC It contains the following section Memory initialization on page 5 2 ...

Page 90: ...memory controller and a memory device to ensure the configuration of both is synchronized Typically PSRAM devices can have the mode register programmed using the address bus only NOR flash memory devices are examples of memory that requires mode register accesses to be carried out using a sequence of accesses using the address and data buses Check the data sheet for the specific memory device you ...

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Page 93: ...rights reserved 5 5 Figure 5 3 SMC and memory initialization sheet 3 of 3 Where x denotes the appropriate chip select 6KHHW 9HULI WKH QHZ WLPLQJV DQG RSHUDWLQJ PRGH QG KHFN IRU FRUUHFW VPFBVUDPBF FOHV B 5HJLVWHU FRQWHQWV HV KHFN IRU FRUUHFW VPFBRSPRGH B 5HJLVWHU FRQWHQWV 1R ...

Page 95: ...escribes the processor signals It contains the following sections About the signals list on page A 2 Clocks and resets on page A 3 AHB signals on page A 4 SMC memory interface signals on page A 5 SMC miscellaneous signals on page A 6 Low power interface on page A 7 Configuration signal on page A 8 Scan chains on page A 9 ...

Page 96: ...A 1 About the signals list This appendix lists the PL241 signals Figure A 1 shows how the signals are grouped Figure A 1 AHB MC PL241 grouping of signals where AHBC AHB Configuration signals 0 3 60 WLH RIIV RZ SRZHU LQWHUIDFH ORFNV DQG UHVHWV 6WDWLF PHPRU LQWHUIDFH RQILJXUDWLRQ VLJQDOV ...

Page 97: ...le A 1 Clocks and resets Name Type Source destination Description hclk Input Clock source AHB clock hresetn Input Reset source AHB clock domain reset smc_aclk Input Clock source SMC AHB clock smc_mclk0 Input Clock source SMC memory clock smc_mclk0n Input Clock source SMC inverted memory clock smc_mreset0n Input Reset source SMC memory clock domain reset ...

Page 98: ...port haddr x 31 0 Input AHB Address of transfer htrans x 1 0 Input AHB Transfer type hwrite x Input AHB Transfer is write or read hsize x 2 0 Input AHB Size of transfer hburst x 2 0 Input AHB Burst type of transfer hprot x 3 0 Input AHB Protection of transfer hwdata x 31 0 Input AHB Write data hmastlock x Input AHB Locked transfer hready x Input AHB System ready hrdata x 31 0 Output AHB Read data ...

Page 99: ... 0 Output Memory Clock smc_add_0 31 0 Output Memory Address smc_cs_n_0 3 0 Output Memory Chip select smc_we_n_0 Output Memory Write enable smc_oe_n_0 Output Memory Output enable smc_adv_n_0 Output Memory Address advance signal smc_baa_n_0 Output Memory Bank address smc_cre_0 Output Memory Configuration register enable smc_bls_n_0 3 0 Output Memory Byte lane strobes smc_data_out_0 31 0 Output Memor...

Page 100: ...ut Tie off Address match for chip select 0 smc_address_mask0_1 7 0 Input Tie off Address mask for chip select 1 smc_address_match0_1 7 0 Input Tie off Address match for chip select 1 smc_address_mask0_2 7 0 Input Tie off Address mask for chip select 2 smc_address_match0_2 7 0 Input Tie off Address match for chip select 2 smc_address_mask0_3 7 0 Input Tie off Address mask for chip select 3 smc_addr...

Page 101: ...estination Description ahb_csysreq Input System controller AHB interfaces low power mode request smc_csysreq Input System controller SMC low power mode request ahb_csysack Output System controller AHB interfaces low power mode acknowledge ahb_cactive Output System controller AHB interfaces active smc_csysack Output System controller SMC low power mode acknowledge smc_cactive Output System controll...

Page 102: ... Limited All rights reserved ARM DDI 0389B A 7 Configuration signal Table A 6 lists the configuration signal Table A 6 Configuration signal Name Type Source destination Description big_endian Input Tie off Big endian mode configuration tie off ...

Page 103: ...an chains SMC scan in for smc_aclk domain smc_si_mclk0 Input Scan chains SMC scan in for smc_mclk0 domain smc_si_mclk0n Input Scan chains SMC scan in for smc_mclk0n domain smc_si_fbclk_in_0 Input Scan chains SMC scan in for smc_fbclk_in_0 domain smc_si_int_0 Input Scan chains SMC scan in for smc_int_0 domain so_hclk Output Scan chains Scan out for hclk domain smc_so_aclk Output Scan chains SMC sca...

Page 105: ...recommends only a subset of the protocol is usually used This subset is defined as the AMBA AHB Lite protocol See also Advanced Microcontroller Bus Architecture and AHB Lite Advanced Microcontroller Bus Architecture AMBA A family of protocol specifications that describe a strategy for the interconnect AMBA is the ARM open standard for on chip buses It is an on chip bus specification that describes...

Page 106: ...t are divisible by four and two respectively AMBA See Advanced Microcontroller Bus Architecture APB See Advanced Peripheral Bus Beat Alternative word for an individual transfer within a burst For example an INCR4 burst comprises four beats See also Burst BE 8 Big endian view of memory in a byte invariant system See also BE 32 LE Byte invariant and Word invariant BE 32 Big endian view of memory in ...

Page 107: ...xed endian data accesses to determine the byte lanes that are active in a transfer One bit of this signal corresponds to eight bits of the data bus Multi master AHB Typically a shared not multi layer AHB interconnect scheme More than one master connects to a single AMBA AHB link In this case the bus is implemented with a set of full AMBA AHB master interfaces Masters that use the AMBA AHB Lite pro...

Page 108: ...sly read from the same field on the same processor Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned For example a word stored at an address that is not divisible by four Undefined Indicates an instruction that generates an Undefined instruction trap See the ARM Architecture Reference Manual for more informati...

Page 109: ...OM when the initialization has been completed Reserved A field in a control register or instruction format is reserved if the field is to be defined by the implementation or produces Unpredictable results if the contents of the field are not zero These fields are reserved for use in future extensions of the architecture or are implementation specific All reserved bits not used by the implementatio...

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Summary of Contents for PrimeCell PL241

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Summary of Contents for PrimeCell PL241

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