2.2
Musca-B1 test chip
The Musca
‑
B1 test chip is based on the SSE
‑
200 subsystem which features two Cortex
‑
M33 processors.
Overview of the Musca-B1 test chip
The Musca
‑
B1 test chip features a memory system, integrated connectivity, sensor interfaces, a clock
generator, and
Serial Configuration Control
(SCC) registers for setting default powerup values.
See the following documentation for more information on the SSE-200 subsystem:
•
Arm
®
CoreLink
™
SSE
‑
200 Subsystem for Embedded Technical Overview
.
•
Arm
®
CoreLink
™
SSE
‑
200 Subsystem for Embedded Technical Reference Manual
.
See the
Arm
®
Musca
‑
B1 Test Chip and Board Technical Reference Manual
for more information.
The following figure shows a high-level view of the architecture of the Musca
‑
B1 test chip.
2 Hardware and software
2.2 Musca-B1 test chip
101311_0000_02_en
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