ARM IM-AD1 User Manual Download Page 56

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Reference Design Example

4-10

ARM DUI 0163B

You must also observe the operating range limits:

Note

The default values for these registers set

CLK1

to 25MHz and

CLK2

to 12MHz.

Table 4-5 LM_OSCx registers

Bits

Name Access

Function

18:16

Read/write

Output divider:

000 = divide by 10

001 = divide by 2

010 = divide by 8

011 = divide by 4

100 = divide by 5

101 = divide by 7

110 = divide by 9

111 = divide by 6.

15:9

RDW

Read/write

Reference divider word. Defines the binary value of
the R[6:0] pins of the clock generator.

8:0

VDW

Read/write

VCO divider word. Defines the binary value of the
V[8:0] pins of the clock generator.

10MHz < 48MHz ·

(V[8:0] +8)

(R[6:0] +2)

R[6:0] < 118

Summary of Contents for IM-AD1

Page 2: ...d its use contained in this document are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this docu...

Page 3: ... guarantee that interference will not occur in a particular installation If this equipment causes harmful interference to radio or television reception which can be determined by turning the equipment off or on you are encouraged to try to correct the interference by one or more of the following measures ensure attached cables do not lie across the card reorient the receiving antenna increase the ...

Page 5: ...le features and architecture 1 4 1 3 Links and LEDs 1 6 1 4 Care of modules 1 7 Chapter 2 Getting Started 2 1 Fitting the interface module 2 2 2 2 Setting up the logic module 2 3 2 3 Running the test software 2 4 Chapter 3 Hardware Reference 3 1 Differences in signal routing between supported logic modules 3 2 3 2 UART interface 3 3 3 3 SPI 3 5 3 4 PWM interface 3 6 3 5 Stepper motor interface 3 8...

Page 6: ...s serial port 4 15 4 6 PWM controller 4 16 4 7 Stepper motor peripheral 4 17 4 8 GPIO 4 21 4 9 SSRAM interface 4 23 4 10 Vectored interrupt controller 4 24 4 11 CAN controller interface 4 26 4 12 ADC and DAC interface 4 27 4 13 Peripheral information block 4 28 Appendix A Signal Descriptions A 1 EXPA A 2 A 2 EXPB A 4 A 3 EXPIM A 6 A 4 Logic analyzer connector A 8 A 5 Multi ICE JTAG A 10 Appendix B...

Page 7: ...ight 2001 2003 All rights reserved vii Preface This preface introduces the Integrator IM AD1 interface module and its user documentation It contains the following sections About this book on page viii Feedback on page xi ...

Page 8: ...ed into the following chapters Chapter 1 Introduction Read this chapter for an introduction to the Integrator IM AD1 interface module This chapter describes the main features of the interface module and identifies the main components Chapter 2 Getting Started Read this chapter for information about preparing the interface module for use with a logic module and Integrator AP motherboard Chapter 3 H...

Page 9: ...and functions where the argument is to be replaced by a specific value monospace bold Denotes language keywords when used outside example code Further reading This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors ARM periodically provides updates and corrections to its documentation See http w...

Page 10: ...ication ARM IHI 0011 ARM Architectural Reference Manual ARM DDI 0100 The following publications provide information about the ARM Developer Suite Getting Started ARM DUI 0064 ADS Tools Guide ARM DUI 0067 ADS Debuggers Guide ARM DUI 0066 ADS Debug Target Guide ARM DUI 0058 ADS Developer Guide ARM DUI 0056 ADS CodeWarrior IDE Guide ARM DUI 0065 The following publication provides information about Mu...

Page 11: ...ook please send email to errata arm com giving the document title the document number the page number s to which your comments apply a concise explanation of your comments General suggestions for additions and improvements are also welcome Feedback on the Integrator IM AD1 If you have any comments or suggestions about this product please contact your supplier giving the product name an explanation...

Page 13: ... 1 Chapter 1 Introduction This chapter introduces the Integrator IM AD1 It contains the following sections About the Integrator IM AD1 on page 1 2 Interface module features and architecture on page 1 4 Links and LEDs on page 1 6 Care of modules on page 1 7 ...

Page 14: ...lication development benchmarking PrimeCell development and testing SoC prototyping The interface module is designed to be mounted on top of the logic module and provides connectivity for peripherals in the logic module FPGA Figure 1 1 on page 1 3 shows the layout of the IM AD1 and identifies the connectors The IM AD1 can be used to implement additional peripherals to aid software development for ...

Page 15: ... Integrator IM AD1 layout CONFIG LED Serial port J18 Logic analyzer J7 GPIO A J17 GPIO B J16 A D Inputs J1 D A Outputs J2 SPI1 J11 SPI2 J13 Stepper motor control J19 and J20 Stepper motor control J21 and J22 PWM J14 and J10 CAN J3A and J3B CONFIG link J8 Multi ICE J9 CAN J3A and J3B ...

Page 16: ...l 12 bit Analog to Digital Converters ADC with 200ksamples s sampling rate and 0 5V buffered inputs two 12 bit Digital to Analog Converter DAC channels with 0 5V outputs two L298 stepper motor drivers configured for bipolar motors two stepper motor control outputs for use with off board drivers two 3A MOSFETs configured as switches for the Pulse Width Modulated PWM outputs RS232 serial transceiver...

Page 17: ...sion connectors and the interface circuits see Chapter 3 Hardware Reference Figure 1 2 Integrator IM AD1 block diagram J3A J3B J19 J23 Stepper motor interfaces D to A converter A to D converter J2 J1 UART interface CAN interfaces J14 J18 EXPA socket EXPIM socket J10 PWMs J17 J16 SERIAL GPIOA GPIOB DC PWM1 DC PWM2 A D IN D A OUT CAN2 CAN1 STEP2 STEP1 EXPB socket J11 J13 SPI1 SPI2 J21 J22 STEP3 STEP...

Page 18: ... link and CONFIG LED Fitting the CONFIG link places all of the modules in the stack on which the interface module is mounted into CONFIG mode This mode enables you to reprogram the FPGA image in the configuration flash on the logic module s using Multi ICE see the user guide for the logic module The CONFIG LED lights to indicate when the stack is in CONFIG mode ...

Page 19: ...ore pulling on both ends of the module at the same time Use the system in a clean environment and avoid debris fouling the connectors on the underside of the PCB Blocked holes can cause damage to connectors on the motherboard or module below Visually inspect the module to ensure that connector holes are clear before mounting it onto another board Observe ElectroStatic Discharge ESD precautions whe...

Page 21: ... 2 1 Chapter 2 Getting Started This chapter describes how to set up and start using the logic module It contains the following sections Fitting the interface module on page 2 2 Setting up the logic module on page 2 3 Running the test software on page 2 4 ...

Page 22: ...gic modules However it only provides interface connections for the logic module immediately beneath it Figure 2 1 shows an example system comprising a core module and logic module attached to an Integrator AP see the Integrator AP User Guide for more details The interface module is installed at the top of the logic module stack Figure 2 1 Assembled Integrator development system ...

Page 23: ...dule 2 Connect Multi ICE unit to J10 on the logic module or J9 on the IM AD1 3 Power up the Integrator system 4 Start the Multi ICE server on your PC and click the Autoconfigure button 5 If you are using an Altera logic module LM EP20K1000E switch 4 of switchpack S1 must be set to the CLOSED position 6 Browse to Install_directory IM AD1 configure 7 Double click the progcards exe program file 8 The...

Page 24: ...ti ICE unit to the core module 2 Power up the Integrator system 3 Start the Multi ICE server and autoconfigure it 4 Browse to Install_directory IM AD1 example software selftest build ads1 1 selftest_Data Release 5 Double click the selftest axf file This starts the ARM debugger and loads the test program 6 Check the debugger is configured to use Multi ICE by selecting Options Configure Target If Mu...

Page 25: ...controllers on the interface module This chapter contains the following sections Differences in signal routing between supported logic modules on page 3 2 UART interface on page 3 3 SPI on page 3 5 PWM interface on page 3 6 Stepper motor interface on page 3 8 GPIO on page 3 12 CAN interface on page 3 14 ADC and DAC interfaces on page 3 18 ...

Page 26: ... follows The LM XCV600E is fitted with a Xilinx FPGA and routes the interface module ABANK 59 0 signals to bank 0 on the FPGA and the BBANK 53 0 signals to bank 1 on the FPGA The LM EP20K600E is fitted with an Altera FPGA and routes the interface module ABANK 59 0 signals to bank 5 on the FPGA and the BBANK 53 0 signals to bank 6 on the FGPA Note These pin assignments are contained in the example ...

Page 27: ...ocket pins as shown in Table 3 1 EXPIM Socket MAX3243E RS232 Transceiver U22 UART_TXD J18 UART_RTS UART_DTR UART_RXD UART_DCD UART_DSR UART_CTS UART_RI SER_TXD SER_RTS SER_DTR SER_RXD SER_DCD SER_DSR SER_CTS SER_RI Table 3 1 Serial interface signal assignment Signal name EXPIM connector Description UART_TXD IM_BBANK41 Transmit data UART_RTS IM_BBANK42 Ready to send UART_DTR IM_BBANK43 Data termina...

Page 28: ...Note The serial interfaces signals operate at RS232 signal levels Serial port functionality corresponds to the DTE configuration Table 3 2 Serial connector signal assignment Pin J18 Type Description 1 SER_DCD Input Data carrier detect 2 SER_RXD Input Receive data 3 SER_TXD Output Transmit data 4 SER_DTR Output Data terminal ready 5 SER_GND Input ground 6 SER_DSR Input Data set ready 7 SER_RTS Outp...

Page 29: ...ree separate SPI devices The SPI signals are routed to two connectors J11 and J13 for ease of connection to different SPI devices although both are connected to the same set of signals Figure 3 3 shows the pinout of the SPI connectors Figure 3 3 SPI interface connector pinout Table 3 3 SPI signals Signal EXPIM connector Description SPI_CLK IM_BBANK31 SPI Clock SPI_TXD IM_BBANK32 SPI transmit data ...

Page 30: ...and the surrounding area of the board becomes very hot when high load currents are used As a PWM output the interfaces can be driven by the DC DC PrimeCell PL160 The DC DC PrimeCell has feedback inputs that negate the drive outputs when LOW These inputs can be used to implement a current limit with external circuitry Table 3 4 shows the assignment of the PWM interface signals to the logic module s...

Page 31: ...reserved 3 7 Table 3 5 shows the signal assignment Table 3 5 PWM connector signals Pin J14 J10 Description 1 PWM1_ V PWM2_ V PWM supply voltage 2 PWM1_SWITCH PWM2_SWITCH PWM switched load connection 3 PWM1_FB PWM2_FB PWM feedback signal 4 PWM_GND PWM_GND PWM ground ...

Page 32: ...cuitry for two bridges and each bridge has separate enable signals The enable signals and four phase drive signals are supplied by a stepper motor controller instantiated in the logic module FPGA see Chapter 4 Reference Design Example The controller logic uses the 4MHz IM_CLK signal divided to provide a step clock The L6506 uses a chopper circuit operating at a frequency of 21kHz to control the cu...

Page 33: ...V Warning The L298 devices U24 and U26 and their heatsinks are very hot when high load currents are used 3 5 2 Stepper motor interface signal summary Table 3 6 shows the assignment of the stepper motor interface signals to the logic module signals on the EXPB connector Ipeak Vref Rsense Ipeak 0 15 x 10 1 5A Table 3 6 Stepper motor interface signals Signal EXPB connector Description STEP1_ENA F0 En...

Page 34: ...or STEP3_O1 and STEP3_O2 STEP3_ENB F13 Enable signal for STEP3_O3 and STEP3_O4 STEP3_PH1 F14 Step3 phase 1 drive signal STEP3_PH2 F15 Step3 phase 2 drive signal STEP3_PH3 F16 Step3 phase 3 drive signal STEP3_PH4 F17 Step3 phase 4 drive signal STEP4_ENA F18 Enable signal for STEP4_O1 and STEP4_O2 STEP4_ENB F19 Enable signal for STEP4_O3 and STEP4_O4 STEP4_PH1 F20 Step4 phase 1 drive signal STEP4_PH...

Page 35: ...per motor connector signals Pin J19 J23 Description 1 STEP1_VSS STEP2_VSS Stepper motor supply 2 STEP1_O1 STEP2_O1 Stepper motor drive output 1 3 STEP1_O2 STEP2_O2 Stepper motor drive output 2 4 STEP1_O3 STEP2_O3 Stepper motor drive output 3 5 STEP1_O4 STEP2_O4 Stepper motor drive output 4 6 STEP_GND STEP_GND Stepper motor ground ...

Page 36: ... GPIOA9 GPIOA12 GND GPIOA15 GPIOA18 GND GND GPIOA21 GND GPIOA24 GND GPIOA27 GPIOA7 GPIOA5 GPIOA8 GPIOA10 GPIOA11 GPIOA13 GPIOA14 GPIOA16 GPIOA17 GPIOA19 GPIOA20 GPIOA22 GPIOA23 GPIOA25 GPIOA26 GPIOA28 GPIOA29 GPIOA31 12V 5v GND GPIOA30 GND 12V 3V3 1 49 J17 5V GPIOB1 GND GPIOB4 GPIOB2 3V3 GPIOB0 GND GPIOB3 2 50 GND GPIOB6 GND GND GPIOB9 GPIOB12 GND GPIOB15 GPIOB18 GND GND GPIOB21 GND GPIOB24 GND GP...

Page 37: ...ts reserved 3 13 The example configuration includes two simple 32 bit GPIO controllers GPIOA 31 0 connect to the EXPIM signals IM_ABANK 31 0 and GPIOB 31 0 connects to the EXPA signals B 31 0 The B 31 0 signals can be monitored on the logic analyzer connector J7 ...

Page 38: ...operate with an 8 bit non multiplexed asynchronous host interface Each of the CAN controllers has a 16MHz crystal that it uses for its internal clocks Figure 3 8 CAN interface architecture EXPIM Socket CAN controller U14 CAN controller U18 CAN_R nW_5V U17 U20 U13 U16 CAN2_nCS_5V CAN1_nCS_5V CAN1_RESET_5V CAN2_RESET_5V CAN1_nDSACK0_5V CAN2_nDSACK0_5V CAN1_nINT_5V CAN2_nINT_5V CAN_A 7 0 _5V CAN_D 7 ...

Page 39: ... from the CAN controllers or directly from the logic module FPGA Table 3 8 shows the assignment of the CAN controller interface signals to the logic module signals on the EXPIM connector Table 3 8 CAN interface signal assignment Signal EXPIM connector Description CAN_A 7 0 IM_BBANK 7 0 CAN address bus CAN_D 7 0 IM_BBANK 8 15 CAN data bus CAN_T R IM_BBANK16 CAN buffer direction control CAN_nOE IM_B...

Page 40: ...top and J3B bottom with CAN1 connecting to J3A Figure 3 9 shows the pin locations for this type of connector Figure 3 9 CAN connector pin locations CAN2_nINT IM_BBANK28 CAN2 interrupt CAN1_RXD IM_BBANK29 CAN1 receive data CAN2_RXD IM_BBANK30 CAN2 receive data Table 3 8 CAN interface signal assignment continued Signal EXPIM connector Description ...

Page 41: ...7 Table 3 9 shows the signal assignment Table 3 9 CAN connector signal assignments Pin J3A J3B 1 Not connected Not connected 2 CAN1_L CAN2_L 3 GND GND 4 Not connected Not connected 5 GND GND 6 GND GND 7 CAN1_H CAN2_H 8 Not connected Not connected 9 Not connected Not connected ...

Page 42: ...owered from a 5V supply and share buffers to interface them to the 3 3V system bus provided by the logic module Figure 3 10 shows the architecture of the ADCs and DACs Figure 3 10 ADC and DAC interface architecture All of the interface signals are routed to the FPGA on the logic module The ADCs and DAC are supported by an AHB interface that is instantiated in the logic module code example supplied...

Page 43: ... 15 0 IM_ABANK 47 32 ADC and DAC data bus AD_T R IM_ABANK48 Buffer direction control AD_nOE IM_ABANK49 Buffer output enable ADC1_nCONV IM_ABANK50 ADC1 conversion start signal ADC1_nCS IM_ABANK51 ADC1 chip select ADC1_nWR IM_ABANK52 ADC1 write strobe ADC1_nRD IM_ABANK53 ADC1 read strobe ADC2_nCONV IM_ABANK54 ADC2 conversion start signal ADC2_nCS IM_ABANK55 ADC2 chip select ADC2_nWR IM_ABANK56 ADC2 ...

Page 44: ...d The op amp buffers cannot drive their outputs lower than 65mV This means input signals less than 130mV will have incorrect ADC values The reference voltage from one of the ADCs is buffered and fed to the reference inputs of the other ADC and the DAC so that all devices share a common reference The GAIN input to the DAC is tied HIGH to configure the output range of the DAC to be 0 to 2xVref Figur...

Page 45: ...Reference ARM DUI 0163B Copyright 2001 2003 All rights reserved 3 21 Figure 3 12 shows the pinout of the DAC interface connector J2 Figure 3 12 DAC connector pinout 5V VOUTA VOUTB 5V GND GND GND GND 1 2 9 10 J2 ...

Page 47: ...example on page 4 2 Example APB register peripheral on page 4 8 UART on page 4 13 SPI chip select register on page 4 14 Synchronous serial port on page 4 15 PWM controller on page 4 16 Stepper motor peripheral on page 4 17 GPIO on page 4 21 SSRAM interface on page 4 23 Vectored interrupt controller on page 4 24 CAN controller interface on page 4 26 ADC and DAC interface on page 4 27 Peripheral inf...

Page 48: ...imeCell HDL source code is provided on the CD The design example supports AHB based designs for Integrator LM XCV600E and LM EP20K600E logic modules 4 1 1 About PrimeCells The ARM PrimeCell peripherals are a range of synthesizable peripherals that are ideally suited for use in ARM based designs The interface module is supplied with PrimeCell peripherals for some of the interfaces on the board and ...

Page 49: ...le 4 1 VHDL file descriptions File Description IMAD1fpga This file is the top level VHDL that instantiates all of the interface for the example The VHDL for the PrimeCell interfaces are not supplied but are available from ARM as separate products AHBDecoder The decoder provides the AHB peripherals with select line generated from the address lines and the module ID position in stack signals from th...

Page 50: ...select signals for each of the APB peripherals APBRegs The APB register peripheral provides memory mapped registers that you can use to configure the two clock generators protected by the LM_LOCK register write to the user LEDs read the user switch inputs produce an interrupt for the LM push button AHBPIB This provides the ROM block that gives the following information about each peripheral base a...

Page 51: ...appropriate memory region see the user guide for your motherboard 4 1 4 Address assignment of logic modules The Integrator motherboards can have more than one logic module mounted on them The base address of each logic module depends on its position in the stack and defines the value of bits 31 28 of the address for all devices on the logic module Table 4 2 on APB peripherals AHB peripherals Core ...

Page 52: ...e memory model for the design is shown in Table 4 2 and assumes that the logic module is mounted in position 0 Table 4 2 Logic module addresses Position in stack Bits 31 28 0 bottom 0xC 1 0xD 2 0xE 3 top 0xF Table 4 3 Integrator IM AD1 memory map Device Address logic module APB registers 0xC0000000 UART0 0xC0100000 SPICS 0xC0200000 SSP 0xC0300000 Reserved 0xC0400000 Reserved 0xC0500000 Reserved 0x...

Page 53: ...001 2003 All rights reserved 4 7 STEPPERB 0xC0C00000 GPIOA 0xC0D00000 GPIOB 0xC0E00000 Reserved 0xC1000000 SSRAM 0xC2000000 VIC 0xC3000000 CAN 0xC4000000 ADC DAC 0xC5000000 PIB 0xCFFFFF00 Table 4 3 Integrator IM AD1 memory map continued Device Address ...

Page 54: ...sses shown in Figure 4 2 on page 4 5 Table 4 4 Logic module registers Offset address Name Type Function 0x0000000 LM_OSC1 Read write Oscillator 1 divisor register 0x0000004 LM_OSC2 Read write Oscillator 2 divisor register 0x0000008 LM_LOCK Read write Oscillator lock register 0x000000C LM_LEDS Read write User LEDs control register 0x0000010 LM_INT Read write Push button interrupt register 0x0000014...

Page 55: ...the value 0x0000A05F to the LM_LOCK register After writing the oscillator register relock them by writing any value other than 0x0000A05F to the LM_LOCK register The reference divider R 6 0 and VCO divider V 8 0 are used to calculate the output frequency as follows Table 4 5 on page 4 10 describes the oscillator register bits Note You can calculate values for the clock control signals using the IC...

Page 56: ...s Bits Name Access Function 18 16 OD Read write Output divider 000 divide by 10 001 divide by 2 010 divide by 8 011 divide by 4 100 divide by 5 101 divide by 7 110 divide by 9 111 divide by 6 15 9 RDW Read write Reference divider word Defines the binary value of the R 6 0 pins of the clock generator 8 0 VDW Read write VCO divider word Defines the binary value of the V 8 0 pins of the clock generat...

Page 57: ...cation that the push button on the logic module has been pressed The output from this register is used to drive an input to the interrupt controller Table 4 7 describes the operation of this register Table 4 6 LM_LOCK register Bits Name Access Function 16 LOCKED Read This bit indicates if the oscillator registers are locked or unlocked 0 unlocked 1 locked 15 0 LOCKVAL Read write Write the value 0x...

Page 58: ...12 Copyright 2001 2003 All rights reserved ARM DUI 0163B 4 2 5 Switches register This register is used to read the setting of the 8 way DIP switch on the logic module A 0 indicates that the associated switch element is closed ON ...

Page 59: ...ights reserved 4 13 4 3 UART The UART used in the design example is the PrimeCell PL011 Refer to the ARM PrimeCell UART PL011 Technical Reference Manual for more information The UART is clocked by the signal CLK2 from the logic module CLK2 is set to 12MHz by default ...

Page 60: ...three chip select signals on the connectors J11 and J13 Writing a 1 causes the associated SPI chip select signal to go LOW Table 4 8 SPI chip select register bit assignment Bit Name Access Function 2 SPICS2 Read write 0 SPI_nCS2 is HIGH 1 SPI_nCS2 is LOW 1 SPICS1 Read write 0 SPI_nCS1 is HIGH 1 SPI_nCS1 is LOW 0 SPICS0 Read write 0 SPI_nCS0 is HIGH 1 SPI_nCS0 is LOW ...

Page 61: ...t The synchronous serial port PrimeCell is used to implement the SPI interface Refer to the ARM PrimeCell Synchronous Serial Port Master and Slave PL022 Technical Reference Manual for information about this device The SSP is clocked by the CLK1 signal from the logic module This clock is set to 25MHz by default ...

Page 62: ...upply the DCDCCLK reference clock It can divide this by 16 32 128 or 304 to provide four possible switching frequencies of 250kHz 125kHz 31 25kHz and 13 158kHz The switching circuitry has turn on and turn off delays that limit the minimum pulse width and can also affect the accuracy of the PWM particularly at the higher switching frequencies between 125kHz to 250kHz The turn on and turn off delays...

Page 63: ...ing register while a previous count continues Write to the STEPxCOUNT and STEPxSPEED register locations first and then follow this with a write to the STEPxCONT register The controller loads the new values into the target registers when the current count completes Table 4 10 Stepper motor registers Offset address Name Access Function 0x0B00000 STEP1CONT Read write Stepper 1 control register 0x0B00...

Page 64: ... 11 Table 4 11 Stepper control register Bits Name Access Function 7 BUSY Read This bit contains 1 when a count is in progress and 0 when the count is complete 6 BUFFERFULL Read This bit contains 1 when the buffer is full and 0 when the buffer is available for a new value to be written An inverted version of this bit is used as an interrupt source 5 DRIVE ENABLE Read write This bit enables and disa...

Page 65: ...rresponding number of steps to be performed 1 SINGLESTEP Read write Write a 1 to this bit to advance the stepper motor by one step The step speed register step count register and bit 2 are ignored 0 DIR Read write This bit controls the direction of rotation The actual direction of rotation clockwise or anticlockwise depends on how the motor is wired to the interface module Table 4 11 Stepper contr...

Page 66: ...ber of steps to advance When the required number of steps are complete the count stops and the register is loaded with the next value 4 7 3 Stepx speed register This register contains a 14 bit value that is used to divide a 10kHz clock signal to regulate the speed of the stepper motor That is the step speed register defines the number of 0 1ms periods between steps Stepx_PH3 Stepx_PH2 Stepx_PH1 St...

Page 67: ...GPIO output bit 0 leave the associated GPIO bit unchanged 4 8 2 Read data input register Read the current state of the GPIO input bits from this location 4 8 3 Data register output clear The GPIO_DATACLR location is used to clear individual GPIO output bits as follows 1 CLEAR the associated GPIO output bit 0 leave the associated GPIO bit unchanged 4 8 4 Read data output pins Read the current state...

Page 68: ... The GPIO_DIRN location is used to set the direction of each GPIO pin as follows 1 pin is an output 0 pin is an input default Figure 4 6 shows the data direction control for one GPIO bit Figure 4 6 GPIO direction control 1 bit Data direction register Data register Read data output Read data input Pin pad ...

Page 69: ...ll rights reserved 4 23 4 9 SSRAM interface The SSRAM interface provides read and write access to the 1MB ZBT SSRAM on the logic module Accesses take two system clock cycles for reads and writes The interface supports word halfword and byte accesses to the SSRAM ...

Page 70: ...interrupt register in the APB register block The interrupt is latched if the push button on the logic module is pressed or if a 1 is written to the push button interrupt register The interrupt is cleared by writing a 0 to the push button interrupt register The UART interrupt is the combined interrupt from the UART PrimeCell Refer to ARM PrimeCell UART PL011 Technical Reference Manual for details o...

Page 71: ...N2 interrupts are interrupt signals from the CAN controller chips The interrupt signals are a combination of interrupts from different sources within the CAN controller Refer to the data sheet for the Bosch CC770 for details of the interrupt sources The ADC1 and ADC2 interrupts are generated from the BUSY signal of the corresponding AD7859 A D converter chip The ADC1 and ADC2 interrupts signal tha...

Page 72: ...ress of the device 4 11 2 CAN reset control register The CAN reset register controls the nRESET signals to the CAN controllers The assignment of the bits in the register is shown in Table 4 15 The CAN controllers are reset by writing a 0 to the associated bit so the nRESET signal goes LOW The default setting of this register after power up is 0 so you must write a 1 before you can read and write t...

Page 73: ... has the signal LDAC tied LOW This means that a value is passed to the DAC as soon as it is written The ADC status register provides you with read only access to the ADC busy signals The bit assignment is shown in Table 4 17 The DACnCLR register provides you with read write access to control the signal nCLR routed to the DAC Write 0 to this register to reset the DAC value to 0 You must write a 1 t...

Page 74: ...ore the revision number in BCD Note Use the ARM executable utility read_pib axf supplied on the IM AD1 CD to display the PIB information Table 4 18 PIB entry format Bits Name Function 31 24 Peripheral Base Bits 27 20 of the peripheral base address Bits 31 28 of the address are defined by the location of the logic module in the stack see Address assignment of logic modules on page 4 5 23 8 Peripher...

Page 75: ...ix describes the Integrator IM AD1 interface connectors and signal connections It contains the following sections EXPA on page A 2 EXPB on page A 4 EXPIM on page A 6 Logic analyzer connector on page A 8 Multi ICE JTAG on page A 10 Note For details of the I O connectors see Chapter 3 Hardware Reference ...

Page 76: ...ons A 2 Copyright 2001 2003 All rights reserved ARM DUI 0163B A 1 EXPA Figure A 1 shows the pin numbers of the EXPA socket The socket is viewed as if looking down through the stack Figure A 1 EXPA socket pin numbering ...

Page 77: ...gnals present on the EXPA connector are described in Table A 1 Table A 1 AHB signal assignment Pin label Signal Description A 31 0 Not used B 31 0 B 31 0 These signals connect to the FPGA on the logic module They are used to carry the GIPOB 31 0 signals C 31 0 Not used D 31 0 Not used ...

Page 78: ...H9 H10 H12 H13 H15 H16 H18 H19 H21 H22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 H26 GND GND F24 F25 F26 GND GND F27 H29 F28 F29 GND GND F30 J0 F31 J8 GND GND J9 J3 J10 J11 J6 GND GND J12 J13 J14 GND J16 J15 3V3 12V 12V 3V3 12V 12V 3V3 12V 12V H24 H25 H27 H28 H30 H31 J1 ...

Page 79: ... F 23 0 F 23 0 Stepper motor controller signals H 31 29 Not used H28 SYSCLK System clock from the logic module H 27 0 Not used J 15 14 Not used J13 nCFGEN Sets motherboard into configuration mode J12 nSRST Multi ICE reset open collector J11 Not used J10 RTCK Returned JTAG test clock J9 Not used J8 nTRST JTAG reset J7 TDO JTAG test data out J6 TDI JTAG test data in J5 TMS JTAG test mode select J4 T...

Page 80: ...IM_B28 GND IM_B29 GND IM_A31 IM_B30 IM_B31 GND IM_B32 GND IM_A34 IM_B33 IM_B34 IM_A37 GND IM_B35 GND IM_B36 IM_B37 GND IM_B38 GND IM_A40 IM_B39 IM_B40 GND IM_B41 GND IM_A43 IM_B42 IM_B43 GND IM_B44 GND IM_A46 IM_B45 IM_B46 IM_A23 IM_A24 IM_A26 IM_A27 IM_A29 IM_A30 IM_A32 IM_A33 IM_A35 IM_A36 IM_A38 IM_A39 IM_A41 IM_A42 IM_A44 IM_A45 IM_A49 GND IM_B47 GND IM_B48 IM_B49 GND IM_B50 GND IM_A52 IM_B51 ...

Page 81: ...utput pins IM_BBANK 53 0 IM_1BANK 53 0 IM_6BANK 53 0 FPGA input output pins EXP 92 85 Not used Not used EXP93 IM_CLK IM_CLK Clock signal from IM AD1 to the logic module FPGA EXP 96 94 Not used Not used EXP97 VCCO_0 VCCO_5 Configurable voltage power supply rail Not used socket EXP98 VCCO_0 VCCO_5 Configurable voltage power supply rail Not used socket EXP185 Not used Not used EXP 189 187 Not used No...

Page 82: ...0 signals used for GPIO B If particular signals must be connected to a logic analyzer the FPGA configuration can be changed to reassign the signal connections Caution If the FPGA configuration is changed to reassign signal connections the GPIO B connections on connector J16 also change Figure A 4 shows the pin numbers of this type of connector Figure A 4 J7 pin locations 1 37 2 38 ...

Page 83: ...nector Table A 4 J7 connector pinout Signal Pin Pin Signal No connect 1 2 No connect GND 3 4 No connect SYSCLK 5 6 CLK_1 B31 7 8 B15 B30 9 10 B14 B29 11 12 B13 B28 13 14 B12 B27 15 16 B11 B26 17 18 B10 B25 19 20 B9 B24 21 22 B8 B23 23 24 B7 B22 25 26 B6 B21 27 28 B5 B20 29 30 B4 B19 31 32 B3 B18 33 34 B2 B17 35 36 B1 B16 37 38 B0 ...

Page 84: ...A 5 Multi ICE JTAG Figure A 5 shows the pinout of the Multi ICE connector J21 For a description of the JTAG signals see the user guide for your logic module Figure A 5 Multi ICE connector pinout 3V3 nTRST TDI TMS TCK RTCK TDO nSRST 3V3 GND GND GND GND GND GND GND GND GND 1 19 2 20 ...

Page 85: ... All rights reserved B 1 Appendix B Mechanical Specification This appendix contains the mechanical specification for Integrator IM AD1 It contains the following section Mechanical information on page B 2 Connector reference on page B 4 ...

Page 86: ... top view The Integrator IM AD1 is designed to be stackable as the top card Figure B 2 on page B 3 shows the dimensions for the connectors on the bottom side of the board as viewed from the top side of the board These connectors carry the signals between the IM AD1 and the logic module All dimensions are in mm 5 59 10 16 10 03 10 34 5 72 7 77 19 56 79 63 101 73 123 83 146 05 171 96 72 64 18 16 16 ...

Page 87: ...MechanicalSpecification ARM DUI 0163B Copyright 2001 2003 All rights reserved B 3 Figure B 2 Bottom board dimensions viewed from top side 171 96 109 98 99 95 138 00 99 95 26 16 9 98 J4 J5 J6 90 23 ...

Page 88: ...P 09P 09P G 15 87 J5 SOLC 150 02 F Q_0 64mm pitch Samtec SOLC 150 02 F Q P A J4 SOLC 150 02 F Q_0 64mm pitch Samtec SOLC 150 02 F Q P A J6 SOLC 130 02 F Q_0 64mm pitch Samtec SOLC 130 02 F Q P A J7 Mictor_38 way Agilent 2 767004 2 J8 2x1_pin_header_0 1 _2W_LINK Toby THS 2 S J9 CON20AP_0 1 _20W_VERT Toby 302 S 20 D1 S1 J10 CON4_3 5mm_4W_RA Weidmuller SL 3 5 4 90G 3 2 SN OR J14 CON4_3 5mm_4W_RA Weid...

Page 89: ...s APB Advanced Peripheral Bus The ARM open standard for lower speed peripherals CAN Controller Area Network DAC Digital to Analog Converter A device that converts digital data into analog level signals FPGA Field Programmable Gate Array GPIO General Purpose Input Output JTAG Joint Test Action Group The committee which defined the IEEE test access port and boundary scan standard Multi ICE Multi ICE...

Page 90: ...ved ARM DUI 0163B SSP Synchronous Serial Port UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus VCO Voltage Controlled Oscillator VIC Vectored Interrupt Controller ZBT SSRAM Zero Bus Turnaround Synchronous Static Random Access Memory ...

Page 91: ... supplied example 4 2 ARM PrimeCell peripherals 4 2 B Block diagram system 1 5 C CAN 4 26 CAN connector 3 16 CAN interface 3 14 4 26 CAN interface signals 3 15 CAN reset register 4 26 Care of modules 1 7 CLK2 signal 4 15 CONFIG link 1 6 Connector identification 1 2 Connectors ADC 3 20 CAN 3 16 DAC 3 21 dimensions B 2 GPIO 3 12 Multi ICE A 10 PWM 3 6 signals A 1 SPI 3 5 stepper 3 10 D DAC connector...

Page 92: ...gnals 3 6 R Read data input pins GPIO 4 21 Read data ouput pins GPIO 4 21 Registers 4 26 ADC and DAC interface 4 27 GPIO_DATACLR 4 21 GPIO_DATAIN 4 21 GPIO_DATAOUT 4 21 GPIO_DATASET 4 21 GPIO_DIRN 4 22 LM_INT 4 8 LM_LEDS 4 8 LM_LOCK 4 8 LM_OSC1 4 8 4 17 LM_OSC2 4 8 LM_SW 4 8 SPI chip select 4 14 step count 4 20 step speed 4 20 stepper control 4 18 S Serial connector 3 4 Serial interface signals 3 ...

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