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ARM Cortex-A9 MBIST Technical Reference Manual Download Page 48

MBIST Instruction Register

3-4

Copyright © 2008 ARM Limited. All rights reserved.

ARM DDI 0414C

Non-Confidential

Restricted Access

3.2

Field descriptions

The following sections describe the MBIR fields:

•

Pattern field, MBIR[57:52]

•

Control field, MBIR[51:46]

•

Read Latency and Write Latency fields, MBIR[42:40] and MBIR[45:43]

•

CPU On field, MBIR[39:36]

•

MaxXAddr and MaxYAddr fields, MBIR[35:32] and MBIR[31:28]

•

DataWord field, MBIR[27:24]

•

ArrayEnables field, MBIR[23:4]

•

ColumnWidth field, MBIR[3:2]

•

CacheSize field, MBIR[1:0]

3.2.1

Pattern field, MBIR[57:52]

The MBIST controller is supplied with industry-standard pattern algorithms and a
bit-line stress algorithm. You can group algorithms together to create a specific memory
test methodology for your product.

Table 3-1 describes the supported algorithms, and

Pattern specification

describes their use. The N values in the table indicate the number of RAM accesses per
address location and give an indication of the test time when using that algorithm.

Table 3-1 Pattern field encoding

Pattern
MBIR[57:52]

Algorithm name

N

Description

b000000

Write Solids

1N

Write a solid pattern to memory

b000001

Read Solids

1N

Read a solid pattern from memory

b000010

Write Checkerboard

1N

Write a checkerboard pattern to memory

b000011

Read Checkerboard

1N

Read a checkerboard pattern from memory

b000100

March C+ (x-fast)

14N

March C+ algorithm, incrementing X-address first

b001011

March C+ (y-fast)

14N

March C+ algorithm, incrementing Y-address first

b000101

Fail Pattern

6N

Tests memory failure detection capability

b000110

Read Write March (x-fast)

6N

Read write march pattern, incrementing X-address first

b000111

Read Write March (y-fast)

6N

Read write march pattern incrementing Y-address first

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Summary of Contents for Cortex-A9 MBIST

Page 1: ...Copyright 2008 ARM Limited All rights reserved ARM DDI 0414C Cortex A9 MBIST Controller Revision r1p0 Technical Reference Manual ...

Page 2: ... faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any inco...

Page 3: ...ARM DDI 0414C Copyright 2008 ARM Limited All rights reserved iii Restricted Access Non Confidential Web Address http www arm com ...

Page 4: ...iv Copyright 2008 ARM Limited All rights reserved ARM DDI 0414C Non Confidential Restricted Access ...

Page 5: ...1 Introduction 1 1 About the MBIST controller 1 2 1 2 MBIST controller interface 1 3 1 3 Product revisions 1 7 Chapter 2 Functional Description 2 1 Functional overview 2 2 2 2 Functional operation 2 15 Chapter 3 MBIST Instruction Register 3 1 About the MBIST instruction register 3 2 3 2 Field descriptions 3 4 Chapter 4 MBIST Datalog Register 4 1 About the MBIST Datalog Register 4 2 4 2 Field descr...

Page 6: ...t 2008 ARM Limited All rights reserved ARM DDI 0414C Non Confidential Restricted Access Appendix A Signal Descriptions A 1 MBIST controller interface signals A 2 A 2 Miscellaneous signals A 4 Appendix B Revisions Glossary ...

Page 7: ... MBISTARRAY bit usage for tag RAMs 2 6 Table 2 5 Tag RAM control 2 8 Table 2 6 MBISTTX signals 2 11 Table 2 7 MBISTRX signals 2 12 Table 2 8 MBIST controller top level I O 2 13 Table 2 9 Data log format 2 18 Table 3 1 Pattern field encoding 3 4 Table 3 2 Go No Go test pattern 3 6 Table 3 3 Control field encoding five LSB bits 3 7 Table 3 4 Read latency field encoding 3 8 Table 3 5 Write latency fi...

Page 8: ... Restricted Access Table 3 11 CacheSize field encoding 3 13 Table A 1 MBIST controller interface signals A 2 Table A 2 MBISTARRAY one hot chip enables A 2 Table A 3 Miscellaneous signals A 4 Table B 1 Differences between issue A and issue B B 1 Table B 2 Differences between issue B and issue C B 1 ...

Page 9: ...Figure 2 2 Data Out for Instruction data RAM and Data data RAM 2 5 Figure 2 3 Data in for Instruction tag RAM 2 6 Figure 2 4 Data out for Instruction tag RAM 2 7 Figure 2 5 Data in for Data tag RAM and SCU tag RAM 2 7 Figure 2 6 Data out for Data tag RAM and SCU tag RAM 2 7 Figure 2 7 Data in for Outer RAM 2 8 Figure 2 8 Data out for Outer RAM 2 8 Figure 2 9 Data in for BTAC RAM 2 9 Figure 2 10 Da...

Page 10: ...e 2 16 Figure 2 18 Start of data log retrieval 2 17 Figure 2 19 End of data log retrieval 2 17 Figure 2 20 Start of bitmap data log retrieval 2 18 Figure 2 21 End of bitmap data log retrieval 2 19 Figure 3 1 MBIST instruction register control unit 3 2 Figure 3 2 MBIST instruction register dispatch unit 3 2 Figure 4 1 MBIST Datalog Register format 4 2 ...

Page 11: ...mited All rights reserved xi Restricted Access Non Confidential Preface This preface introduces the Cortex A9 MBIST Controller Technical Reference Manual It contains the following sections About this book on page xii Feedback on page xvi ...

Page 12: ...BIST controller to test the RAM blocks used by the Cortex A9 processor The AXI protocol is not specified but some familiarity with AXI is assumed Using this book This book is organized into the following chapters Chapter 1 Introduction Read this for an introduction to MBIST technology Chapter 2 Functional Description Read this for a description of the Cortex A9 processor interface to the MBIST con...

Page 13: ...otes introduces special terminology denotes internal cross references and citations bold Highlights interface elements such as menu names Denotes signal names Also used for terms in descriptive lists where appropriate monospace Denotes text that you can enter at the keyboard such as commands file and program names and source code monospace Denotes a permitted abbreviation for a command or option Y...

Page 14: ...Key to timing diagram conventions Signals The signal conventions are Signal level The level of an asserted signal depends on whether the signal is active HIGH or active LOW Asserted means HIGH for active HIGH signals LOW for active LOW signals Lower case n At the start or end of a signal name denotes an active LOW signal Prefix A Denotes global Advanced eXtensible Interface AXI global and address ...

Page 15: ...l signals Prefix W Denotes AXI write data channel signals Further reading This section lists publications by ARM and by third parties See http infocenter arm com for access to ARM documentation ARM publications This book contains information that is specific to this product See the following documents for other relevant information Cortex A9 Technical Reference Manual ARM DDI 0388 Cortex A9 Config...

Page 16: ...his product contact your supplier giving the product name The product revision or version An explanation with as much information as you can provide Include symptoms if appropriate Feedback on this book If you have any comments on this book send e mail to errata arm com giving the title the number the relevant page number s to which your comments apply a concise explanation of your comments ARM al...

Page 17: ...1 1 Restricted Access Non Confidential Chapter 1 Introduction This chapter describes the purpose of the MBIST controller It contains the following sections About the MBIST controller on page 1 2 MBIST controller interface on page 1 3 Product revisions on page 1 7 ...

Page 18: ...s You must only use the MBIST controller with the Cortex A9 processor to perform memory testing of the Cortex A9 RAMs MBIST mode takes priority over all other modes for example SCAN in that the Cortex A9 RAMs are only accessible to the MBIST controller when MBIST mode is activated with the MBISTENABLE pin You must keep the MBISTENABLE signal LOW during functional mode and the AXI interfaces LOW du...

Page 19: ...r wiring diagram Figure 1 3 on page 1 4 shows the traditional method of accessing RAMs for MBIST MBISTDATAIN nRESET MBISTENABLE MBISTDSHIFT MBISTRUN MBISTSHIFT MBISTRESULT 5 0 nRESET CLK CLK MBISTDOUTDATA 255 0 nRESET MBISTENABLE MBISTDSHIFT MBISTRUN MBISTSHIFT MBISTDATAIN MBISTRESULT 5 0 MBISTARRAY 19 0 MBISTBE 25 0 MBISTADDR 10 0 MBISTINDATA 63 0 MBISTARRAY 19 0 MBISTBE 25 0 MBISTADDR 10 0 MBIST...

Page 20: ...the maximum operating frequency it is not suitable for high performance designs Instead the MBIST controller uses an additional input to the existing functional multiplexors without reducing maximum operating frequency Figure 1 4 on page 1 5 shows the six pipeline stages used to access the RAM arrays DataIn BistDataIn 0 1 0 1 Address BistAddress 0 1 CE BistCE 0 1 WE BistWE BistMode RAM DataOut Bis...

Page 21: ...T interface MBISTARRAY MBISTINDATA MBISTBE MBISTADDR MBISTENABLE RAM MBISTENABLE data1 datan Other CPUs Other SCU MBISTDOUT CE Din BWE ADDR Qout Functional path Pipeline stages 1 2 3 4 5 6 denotes a D type flip flop unless otherwise indicated datan data1 data1 datan CK ___ Active high D Type transparent latch data1 datan MBISTWRITEEN data1 datan WE ...

Page 22: ...rocessor MBIST interface signals Name Type Description nRESET Input Global active LOW reset signal CLK Input Active HIGH clock signal This clock drives the Cortex A9 processor logic MBISTOUTDATA 255 0 Output Data out bus from all cache RAM blocks MBISTENABLE Input Select signal for cache RAM array This signal is the select input to the multiplexors that access the cache RAM arrays for test When as...

Page 23: ...revisions This section summarizes the differences in functionality between the releases of this MBIST controller r0p0 r1p0 There are no functionality changes You must use the correct corresponding revision of MBIST controller with corresponding processor revision For example use an r1p0 processor with an r1p0 MBIST controller ...

Page 24: ...Introduction 1 8 Copyright 2008 ARM Limited All rights reserved ARM DDI 0414C Non Confidential Restricted Access ...

Page 25: ...r contains a functional overview of the MBIST controller implementation and a description of its functional operation It includes timing sequences for loading instructions starting the MBIST engine detecting failures and retrieving the data log It contains the following sections Functional overview on page 2 2 Functional operation on page 2 15 ...

Page 26: ... testing the Cortex A9 processor compiled RAMs You can also choose to design your own MBIST controller For the MBIST to run correctly on the Cortex A9 processor if the dormant power off wrappers are implemented you have to set the signals on the Cortex A9 processor interface as shown in Table 2 1 Table 2 2 shows the interfaces between the MBIST controller and the RAMs that MBIST tests Table 2 1 Co...

Page 27: ... 12 25 0 25 0 25 0 8 0 Data tag RAM array 1 11 25 0 25 0 57 32 8 0 Data tag RAM array 0 11 25 0 25 0 25 0 8 0 TLB RAM array 1 10 60 0 60 0 5 0 TLB RAM array 0 9 60 0 60 0 5 0 Global History Buffer arrays 0 1 2 3 8 15 0 15 0 15 0 8 0 Instruction data RAM array 7 way 3 high 7 63 32 63 32 10 0 Instruction data RAM array 6 way 3 low 7 31 0 31 0 10 0 Instruction data RAM array 5 way 2 high 6 63 32 63 3...

Page 28: ...n page 2 10 Instruction data RAM array 2 way 1 low 5 31 0 31 0 10 0 Instruction data RAM array 1 way 0 high 4 63 32 63 32 10 0 Instruction data RAM array 0 way 0 low 4 31 0 31 0 10 0 Instruction tag RAM array 3 3 21 0 53 32 8 0 Instruction tag RAM array 2 3 21 0 21 0 8 0 Instruction tag RAM array 1 2 21 0 53 32 8 0 Instruction tag RAM array 0 2 21 0 21 0 8 0 BTAC RAM target array 1 1 63 32 63 32 7...

Page 29: ...re 2 1 and Figure 2 2 Figure 2 1 Data In for Instruction data RAM and Data data RAM Figure 2 2 Data Out for Instruction data RAM and Data data RAM Instruction data RAMs have a word write enable controlled by MBISTWRITEEN when in BIST mode Data data RAMs have a byte write enable controlled by MBISTBE 3 0 as shown in Table 2 3 MBISTINDATA 63 0 Data in 31 0 for array n 1 Data in 31 0 for array n 0 31...

Page 30: ...AY bits used to select each tag RAM Figure 2 3 and Figure 2 4 on page 2 7 show the data mapping on MBISTINDATA and MBISTOUTDATA buses for Instruction tag RAM Figure 2 3 Data in for Instruction tag RAM 1 Byte 1 bits 15 8 2 Byte 2 bits 23 16 3 Byte 3 bits 31 24 Table 2 4 MBISTARRAY bit usage for tag RAMs MBISTARRAY bits Description 3 2 Select the Instruction tag array 12 11 Select the Data tag array...

Page 31: ...0 for array n 1 Data out 21 0 for array n Data out 21 0 for array n 1 Data out 21 0 for array n Data out 21 0 for array n 1 Data out 21 0 for array n Data out 63 0 for CPU 3 Data out 63 0 for CPU 2 Data out 63 0 for CPU 1 Data out 63 0 for CPU 0 Unused MBISTINDATA 63 0 Data in 25 0 for array n Unused 31 32 0 57 58 63 25 26 MBISTOUTDATA 255 0 63 0 127 128 191 192 255 64 Data out 25 0 for array n 1 ...

Page 32: ...out for Outer RAM Branch Target Address Cache RAM Branch Target Address Cache BTAC RAMs consist of two arrays one for control and one for target The target array is always 32 bits wide MBISTARRAY 1 0 selects the BTAC array They are word writable controlled by MBISTWRITEEN when in BIST mode Table 2 5 Tag RAM control RAM type Write enable MBISTBE bits SCU tag RAM Bit write enable 22 0 Data tag RAM B...

Page 33: ... on page 2 10 show the data mapping on MBISTINDATA and MBISTOUTDATA buses for TLB RAM Figure 2 11 Data in for TLB RAM Data in 27 0 control array MBISTINDATA 63 0 Data in 31 0 target array 0 63 30 62 27 Unused 31 MBISTOUTDATA 255 0 63 0 127 128 191 192 255 64 Data out 27 0 for control array Data out 63 0 for CPU3 Data out 63 0 for CPU2 Data out 63 0 for CPU1 Data out 63 0 for CPU0 Data out 31 0 for...

Page 34: ...controlled by MBISTBE 11 0 when in BIST mode Figure 2 13 shows the data mapping on the MBISTINDATA bus for GHB RAM Figure 2 13 Data in for GHB RAM 2 1 3 MBIST controller implementation The MBIST controller block shown in Figure 2 14 on page 2 11 contains two major blocks MBIST controller dispatch unit MBISTOUTDATA 255 0 0 128 191 192 255 Data out 60 0 Data out 63 0 for CPU3 Data out 63 0 for CPU2 ...

Page 35: ...he MBIST controller and the dispatch unit communicate using the following signals MBISTTX 11 0 This signal is an output of the MBIST controller that goes to the dispatch unit Table 2 6 shows the signals MBIST controller Dispatch unit MBIST controller block MBISTTX 11 0 MBISTRX 5 0 Table 2 6 MBISTTX signals MBISTTX bit Description 0 Reset address 1 Increment address 2 Access sacrificial row used du...

Page 36: ...controller The behavior of MBISTRX 5 0 is ARM specific and is intended for use only with the MBIST controller The address expire signal is set when both the row and column address counters expire Table 2 7 shows the signals 9 Enable bitmap mode 10 Increment go nogo dataword selection 11 Latency stall control Table 2 7 MBISTRX signals MBISTRX bit Description 0 Real time error flag 1 Shadow pipeline...

Page 37: ...MBIST tests to initialize the arrays to a required background the ATPG test procedures must assert SE during all test setup cycles in addition to load unload Any clocking during IDDQ capture cycles must have array chip select signals constrained MBISTRESULT 5 0 During tests the MBISTRESULT 1 signal indicates failures You can operate using two modes by configuring bit 5 of the engine control sectio...

Page 38: ...or each failed compare If bit 5 is not set the MBISTRESULT 1 signal is sticky and is asserted from the first failure until the end of the test At the completion of the test the MBISTRESULT 0 signal goes HIGH The MBISTRESULT 5 2 signal indicates that an address expire for CPU0 has occurred and enables you to measure sequential progress through the test algorithms ...

Page 39: ...n by your ATE the faster clock relates to the clock driven by an on chip Phase Locked Loop PLL If you do not have an on chip PLL both clocks relate to the clock driven by your ATE Timing diagrams in the following sections show the procedures for operating the MBIST controller Instruction load Starting MBIST on page 2 16 Failure detection on page 2 16 Data log retrieval on page 2 16 Instruction loa...

Page 40: ... MBISTRESULT 0 flag goes HIGH two cycles later Figure 2 17 Detecting an MBIST failure Note To ensure that the ATE can observe a failure at test speed specify a sticky fail in the MBIST instruction See Control field MBIR 51 46 on page 3 7 Data log retrieval During a test the MBIST controller automatically logs the first detected failure If required you can retrieve the data log at the end of the te...

Page 41: ...by putting the PLL in bypass mode and driving MBISTRUN LOW as Figure 2 18 shows To begin shifting out the data log on MBISTRESULT 5 2 drive MBISTDSHIFT HIGH The MBISTRESULT 1 flag goes LOW two cycles after MBISTRUN goes LOW Data begins shifting out on MBISTRESULT 5 2 two cycles after MBISTDSHIFT goes HIGH Figure 2 18 Start of data log retrieval When the last data log bit shifts out drive MBISTDSHI...

Page 42: ...re 2 20 shows Figure 2 20 Start of bitmap data log retrieval After you finish shifting and drive MBISTDSHIFT LOW the controller then resumes testing where it stopped as Figure 2 21 on page 2 19 shows This process continues until the test algorithm completes A fault can cause a failure to occur several times during a given test algorithm The fault might be logged multiple times depending on the num...

Page 43: ...right 2008 ARM Limited All rights reserved 2 19 Restricted Access Non Confidential Figure 2 21 End of bitmap data log retrieval Loading a new instruction resets bitmap mode D 76 D 77 D 78 CLK MBISTRESULT 1 MBISTDSHIFT MBISTRESULT 5 2 MBISTRUN ...

Page 44: ...Functional Description 2 20 Copyright 2008 ARM Limited All rights reserved ARM DDI 0414C Non Confidential Restricted Access ...

Page 45: ...nfidential Chapter 3 MBIST Instruction Register This chapter describes how to use the MBIST Instruction Register MBIR to configure the mode of operation of the MBIST controller It contains the following sections About the MBIST instruction register on page 3 2 Field descriptions on page 3 4 ...

Page 46: ...he control unit part of the MBIR Figure 3 1 MBIST instruction register control unit The control unit contains the following fields Pattern Specifies the test algorithm Control Specifies MBIST mode of operation and sticky or nonsticky fail flag Write latency Specifies the number of cycles to enable a RAM write Read latency Specifies the number of cycles to enable a RAM read Figure 3 2 shows the dis...

Page 47: ...axYAddr Specifies the number of bits in the Y address counter DataWord Data seed to be used during test These 4 bits are replicated 16 times to form 64 bits of data ArrayEnables Specifies the RAM under test ColumnWidth Specifies 4 8 16 or 32 columns per block of RAM CacheSize Specifies a cache size of 16KB 32KB or 64KB Field descriptions on page 3 4 describes the MBIR fields in more detail ...

Page 48: ... methodology for your product Table 3 1 describes the supported algorithms and Pattern specification on page 3 5 describes their use The N values in the table indicate the number of RAM accesses per address location and give an indication of the test time when using that algorithm Table 3 1 Pattern field encoding Pattern MBIR 57 52 Algorithm name N Description b000000 Write Solids 1N Write a solid...

Page 49: ...by alternating the supplied data seed and its inverse Read Checkerboard This reads back the physical checkerboard pattern created by alternating the supplied data seed and its inverse For the next set of patterns the following notation describes the algorithm 0 represents the data seed 1 represents the inverse data seed w indicates a write operation r indicates a read operation indicates that the ...

Page 50: ...scription row 0 indicates a read or write of the data seed to the sacrificial row this is always the first row of the column being addressed w0 r0 w0 w0 row 0 6 r0 5 w0 row 0 r0 r0 Go No Go If you do not want to implement your own memory test strategy use the Go No Go test pattern that performs the algorithms that Table 3 2 shows This test suite provides a comprehensive test of the arrays The seri...

Page 51: ...BIR 45 43 The Read Latency and Write Latency fields of the MBIR are used to specify the read and write latency of the RAM under test Read and write latencies are the numbers of cycles that the RAM requires to complete read and write operations For example in a write to a RAM with a write latency of two cycles the RAM inputs are valid for a single cycle The next cycle is a NOP cycle with the chip e...

Page 52: ...r write operations 3 2 4 CPU On field MBIR 39 36 The CPU On field controls data comparison for the CPUs under test Table 3 4 Read latency field encoding Read Latency MBIR 42 40 Number of cycles per read operation b000 1 b001 2 b010 3 b011 4 b100 5 b101 6 b110 7 b111 8 Table 3 5 Write latency field encoding Write Latency MBIR 45 43 Number of cycles per write operation b000 1 b001 2 b010 3 b011 4 b1...

Page 53: ...epresents the topology of the physical implementation of the RAM more accurately The dimensions are controlled by two separate address counters the X address counter and the Y address counter One counter can be incremented or decremented only when the other counter has expired The chosen test algorithm determines the counter that moves faster Use this procedure to determine how many bits to assign...

Page 54: ... settings MaxYAddr The MaxYAddr field specifies the number of Y address counter bits to use during test Table 3 8 shows the MaxYAddr settings Table 3 7 MaxXAddr field encoding MaxXAddr MBIR 35 32 Number of counter bits b0010 Unsupported b0010 2 b0011 3 b0100 4 b0101 5 b0110 6 b0111 7 b1000 8 b1001 9 b1010 10 b1010 Reserved Table 3 8 MaxYAddr field encoding MaxYAddr MBIR 31 28 Number of counter bit...

Page 55: ...rch or bit line stress tests The MBIST engine replicates the four bits of data 16 times to give the full 64 bits of data required on the MBISTDIN 63 0 port of the MBIST interface 3 2 7 ArrayEnables field MBIR 23 4 Table 3 9 shows how each bit in the ArrayEnables field selects the cache RAM array to be tested You can select only one array at a time Selecting multiple arrays produces unpredictable b...

Page 56: ...tion data RAM way 0 block 0 and 1 b00000000000000100000 Instruction data RAM way 1 block 2 and 3 b00000000000001000000 Instruction data RAM way 2 block 4 and 5 b00000000000010000000 Instruction data RAM way 3 block 6 and 7 b00000000000100000000 Global History Buffer b00000000001000000000 TLB RAM array 0 b00000000010000000000 TLB RAM array 1 b00000000100000000000 Data tag RAM arrays 0 and 1 b000000...

Page 57: ...equired to select them 3 2 9 CacheSize field MBIR 1 0 The CacheSize field specifies the size of the cache in your implementation of the module Table 3 11 shows the supported cache sizes Table 3 10 ColumnWidth field encoding ColumnWidth MBIR 3 2 Number of columns Number of address bits b00 4 2 b01 8 3 b10 16 4 b11 32 5 Table 3 11 CacheSize field encoding CacheSize MBIR 1 0 Cache size b00 16KB b10 3...

Page 58: ...MBIST Instruction Register 3 14 Copyright 2008 ARM Limited All rights reserved ARM DDI 0414C Non Confidential Restricted Access ...

Page 59: ...ights reserved 4 1 Restricted Access Non Confidential Chapter 4 MBIST Datalog Register This chapter describes the MBIST Datalog Register It contains the following sections About the MBIST Datalog Register on page 4 2 Field descriptions on page 4 3 ...

Page 60: ...he register is 79 bits long for each CPU Figure 4 1 shows the register format Figure 4 1 MBIST Datalog Register format Field descriptions on page 4 3 describes the register fields in detail The datalogs for all CPUs are dumped in parallel through MBISTRESULT 5 2 with MBISTRESULT 5 for CPU3 MBISTRESULT 4 for CPU2 MBISTRESULT 3 for CPU1 MBISTRESULT 2 for CPU0 Failing address Failing CPU data out Exp...

Page 61: ...Non Confidential 4 2 Field descriptions These are the fields in the MBIST Datalog Register Datalog 78 68 11 bits that contain the failing address Datalog 67 4 64 bits that contain an XOR between failing data and correct data All bits at1 b1 are failing Datalog 3 0 4 bits that contain the expected data seed ...

Page 62: ...MBIST Datalog Register 4 4 Copyright 2008 ARM Limited All rights reserved ARM DDI 0414C Non Confidential Restricted Access ...

Page 63: ...ts reserved A 1 Restricted Access Non Confidential Appendix A Signal Descriptions This appendix describes the MBIST controller signals It contains the following sections MBIST controller interface signals on page A 2 Miscellaneous signals on page A 4 ...

Page 64: ...ATA 63 0 Output MBIST data in to Cortex A9 processor MBISTBE 25 0 Output MBIST write enable MBISTWRITEEN Output Global write enable Table A 2 MBISTARRAY one hot chip enables MBISTARRAY bit RAM name 0 BTAC RAM control array 0 and target array 0 1 BTAC RAM control array 1 and target array 1 2 Instruction tag RAM arrays 0 and 1 3 Instruction tag RAM arrays 2 and 3 4 Instruction data RAM way 0 blocks ...

Page 65: ...fidential 13 Data data RAM way 0 blocks 0 and 4 14 Data data RAM way 1 blocks 1 and 5 15 Data data RAM way 2 blocks 2 and 6 16 Data data RAM way 3 blocks 3 and 7 17 Douter RAM 18 SCU tag RAM arrays 0 and 1 19 SCU tag RAM arrays 2 and 3 Table A 2 MBISTARRAY one hot chip enables continued MBISTARRAY bit RAM name ...

Page 66: ...ellaneous signals Table A 3 Miscellaneous signals Signal Type Description nRESET Input Global active LOW reset signal CLK Input Clock MBISTDATAIN Input Serial data in MBISTDSHIFT Input Data log shift MBISTRESETN Input MBIST reset MBISTRESULT 5 0 Output Output status bus MBISTRUN Input Run MBIST test MBISTSHIFT Input Instruction shift MBISTENABLE Input MBIST mode enable ...

Page 67: ...changes Table B 2 Differences between issue B and issue C Change Location Updated description about the MBIST controller About the MBIST controller on page 1 2 Updated MBIST controller signals Figure 1 2 on page 1 3 Updated MBIST controller interface signals Figure 1 3 on page 1 4 Updated signal names and settings Table 2 1 on page 2 2 Updated bit information for the MBIST controller interfaces Ta...

Page 68: ...ata out for Instruction tag RAM Figure 2 4 on page 2 7 Clarified Tag RAM control Table 2 5 on page 2 8 Updated TLB RAM description TLB RAM on page 2 9 Updated Branch Target Address Cache RAM description Branch Target Address Cache RAM on page 2 8 Table B 2 Differences between issue B and issue C continued Change Location ...

Page 69: ...ntry See also Cache terminology diagram on the last page of this glossary Byte An 8 bit data item Cache A block of on chip or off chip fast access memory locations situated between the Cortex A9 processor and main memory used for storing and retrieving copies of often used instructions and or data This is done to greatly increase the average speed of memory accesses and so improve Cortex A9 proces...

Page 70: ...and main memory used for storing and retrieving copies of often used instructions This is done to greatly increase the average speed of memory accesses and so improve Cortex A9 processor performance Tag The upper portion of a block address used to identify a cache line within a cache The block address from the CPU is compared with each tag in a set in parallel to determine if the corresponding lin...

Page 71: ...erved Glossary 3 Restricted Access Non Confidential Block address Tag Tag Tag Tag Index Word Hit way number Read data way that corresponds 3 1 Tag 0 0 2 1 3 4 5 6 7 n Byte Cache way Cache set m 1 2 0 Cache line 2 Line number Word number Cache tag RAM Cache data RAM ...

Page 72: ...Glossary Glossary 4 Copyright 2008 ARM Limited All rights reserved ARM DDI 0414C Non Confidential Restricted Access ...

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