Arm
®
CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Signal Descriptions
A.3 APB completer interface signals
The GFC-200 provides two APB completer interfaces. One interface for the primary domain and
one interface for the secondary domain. The primary domain can access some extra registers that
enable the primary APB requester to control the Flash partitioning behavior. The primary domain
can also access the registers in the process-specific part.
Primary APB completer interface signals, APB 0
The following table shows the APB completer interface signals that the primary APB requester
connects to.
Table A-3: Primary APB completer interface (APB 0) signals
Signal name
Direction Description
psel_s0
Input
Completer select signal.
penable_s0
Input
Indicates the start of the second cycle of an APB transfer.
paddr_s0[12:0]
Input
Address bus.
paddr_s0[12]
selects either the internal or an external register bank:
0 = Internal registers.
1 = External registers in the process-specific part.
pstrb_s0[3:0]
Input
Write strobe port. Each bit refers to a byte in the
pwdata_s0
signal.
pwrite_s0
Input
APB transfer direction.
pwdata_s0[31:0]
Input
32-bit write data bus.
pwakeup_s0
Input
The APB bridge sets this signal HIGH when a transfer is in progress on the primary APB interface, APB 0.
prdata_s0[31:0]
Output
32-bit read data bus.
Reset value =
0x0
.
pready_s0
Output
Driven LOW when extra wait states are required to complete access to the external registers.
Reset value =
0b0
.
pslverr_s0
Output
Driven HIGH when an error response is received from an access to the external registers.
Reset value =
0b0
.
Secondary APB completer interface signals, APB 1
The following table shows the APB completer interface signals that the secondary APB requester
connects to.
Table A-4: Secondary APB completer interface (APB 1) signals
Signal name
Direction Description
psel_s1
Input
Completer select signal.
penable_s1
Input
Indicates the start of the second cycle of an APB transfer.
paddr_s1[11:0]
Input
Address bus.
pstrb_s1[3:0]
Input
Write strobe port. Each bit refers to a byte in the
pwdata_s1
signal.
pwrite_s1
Input
APB transfer direction.
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