ARM CoreLink GFC-200 Technical Reference Manual Download

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Arm

CoreLink™ GFC-200 Generic Flash Controller

Technical Reference Manual

Document ID: 101484_0000_01_en

Issue: 01

Programmers Model

Attributes

Oﬀset

0xFF8

Type

Read only.

Reset

0x05

Width

The following ﬁgure shows the bit assignments.

Figure 4-35: CIDR2 register bit assignments

8 7 0

PRMBL_2

Reserved

The following table shows the register bit assignments.

Table 4-31: CIDR2

Bits

Name

Function

[31:8]

Reserved, returns 0.

[7:0]

PRMBL_2

Preamble[2]. Returns segment 2 of the component identiﬁcation code.

4.4.31 Component ID register 3, CIDR3

The CIDR3 register returns byte[3] of the component ID. A debugger during system discovery can

use the component ID to discover that the peripheral contains a programmers register block.

The CIDR3 register characteristics are:

Usage constraints

There are no usage constraints.

Conﬁgurations

Available in all conﬁgurations.

Attributes

Oﬀset

0xFFC

Type

Read only.

Non-Conﬁdential

Page

Summary of Contents for CoreLink GFC-200

Page 1: ...Arm CoreLink GFC 200 Generic Flash Controller Revision r0p0 Technical Reference Manual Non Conﬁdential Copyright 2019 2022 Arm Limited or its aﬃliates All rights reserved Issue 01 101484_0000_01_en ...

Page 2: ...s document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents THIS DOCUMENT IS PROVIDED AS IS ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES EXPRESS IMPLIED OR STATUTORY INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF MERCHANTABILITY SATISFACTORY QUALITY...

Page 3: ... its subsidiaries in the US and or elsewhere All rights reserved Other brands and names mentioned in this document may be the trademarks of their respective owners Please follow Arm s trademark usage guidelines at https www arm com company policies trademarks Copyright 2019 2022 Arm Limited or its aﬃliates All rights reserved Arm Limited Company 02557590 registered in England 110 Fulbourn Road Cam...

Page 4: ...and our industry have used language that can be oﬀensive Arm strives to lead the industry and create change Previous issues of this document included language that can be oﬀensive We have replaced this language See B Revisions on page 90 To report oﬀensive language in this document email terms arm com Copyright 2019 2022 Arm Limited or its aﬃliates All rights reserved Non Conﬁdential Page 4 of 90 ...

Page 5: ...escription 16 3 1 Internal structure 16 3 2 Interfaces 17 3 2 1 AHB Lite subordinate interface 18 3 2 2 Primary APB completer interface 20 3 2 3 Secondary APB completer interface 21 3 2 4 APB requester interface 22 3 2 5 GFB interface 22 3 2 6 Q Channel interface for clock 24 3 2 7 Q Channel interface for power 24 3 2 8 P Channel controller interface 25 3 2 9 Partition conﬁguration interface 25 3 ...

Page 6: ... 4 4 13 Partition ownership status register PART_CTRL_RW_STATUS 55 4 4 14 Partition control read only status register PART_CTRL_RO_STATUS 56 4 4 15 Partition control read status register PART_CTRL_RD_STATUS 57 4 4 16 Partition conﬁguration mode request register PART_CONFIG_MODE_REQ 58 4 4 17 Partition conﬁguration mode status register PART_CONFIG_MODE_STATUS 59 4 4 18 Access violation response reg...

Page 7: ...cess rights 80 4 8 Flash macro power control 81 A Signal Descriptions 82 A 1 System interface signals 82 A 2 AHB Lite subordinate interface signals 82 A 3 APB completer interface signals 84 A 4 APB requester interface signals 85 A 5 GFB manager interface signals 86 A 6 Partition control interface signals 87 A 7 Q Channel interface signals 88 A 8 P Channel controller interface signals 89 A 9 DFT si...

Page 8: ... documents Glossary The Arm Glossary is a list of terms used in Arm documentation together with deﬁnitions for those terms The Arm Glossary does not contain terms that are industry standard unless the Arm meaning diﬀers from the generally accepted meaning See the Arm Glossary for more information developer arm com glossary Typographic conventions Convention Use italic Citations bold Interface elem...

Page 9: ...irements for the system Not following these requirements will result in system failure or damage An important piece of information that needs your attention A useful tip that might make it easier better or faster to perform a task A reminder of something important that relates to the information you are reading Timing diagrams The following ﬁgure explains the components used in timing diagrams Var...

Page 10: ...cument ID Licensee only AMBA APB Protocol Speciﬁcation Version 2 0 IHI 0024 No AMBA 3 AHB Lite Protocol Speciﬁcation v1 0 IHI 0033A No AMBA Low Power Interface Speciﬁcation Arm Q Channel and P Channel Interfaces IHI 0068 No Arm CoreLink GFC 200 Generic Flash Controller Conﬁguration and Integration Manual 101485 Yes AMBA Generic Flash Bus Protocol Speciﬁcation IHI 0083 Yes Table 1 3 Other publicati...

Page 11: ...the eFlash memory The GFC 200 provides functions that relate only to services for the system side of the Flash controller The GFC 200 cannot communicate directly with the eFlash macro Therefore the GFC 200 must be integrated with a process speciﬁc part that connects to and communicates with the eFlash macro The process speciﬁc part of the Flash controller is part of the Flash subsystem in your SoC...

Page 12: ...ndary domain Secure system primary domain GFC 200 Generic Flash Controller Process speciﬁc part eFlash macro Generic Flash Bus Flash interface 2 2 Compliance The GFC 200 interfaces are compliant with Arm speciﬁcations and protocols The GFC 200 is compliant with the AMBA GFB protocol See the AMBA Generic Flash Bus Protocol Speciﬁcation Copyright 2019 2022 Arm Limited or its aﬃliates All rights rese...

Page 13: ...arameter controls the size of the partitions AMBA AHB Lite interface Read only access to the embedded Flash Conﬁgurable data width Burst support Low latency Primary APB completer interface Write and erase access to the embedded Flash Debug read access to the embedded Flash Control port for GFC 200 and the eFlash macro Interrupt capability for long running commands Access to internal registers and ...

Page 14: ...g the FWDATA_WIDTH parameter The size of the partitions in Flash memory by using the PARTITION_SIZE parameter 2 5 Test features GFC 200 provides components that comprise a Flash model that simulates the behavior of the process speciﬁc part and the attached embedded Flash The GFC 200 deliverables include an Out of Box OoB execution testbench You can use the execution testbench to check that the del...

Page 15: ...e device that you use The TRM complements architecture and protocol speciﬁcations and relevant external standards It does not duplicate information from these sources Conﬁguration and Integration Manual The CIM describes The available build conﬁguration options How to conﬁgure the RTL with the build conﬁguration options How to integrate GFC 200 into an SoC How to implement GFC 200 into your design...

Page 16: ... a description of the GFC 200 Generic Flash Controller functions 3 1 Internal structure GFC 200 comprises several submodules The following ﬁgure shows the internal high level structure of an example system that integrates GFC 200 with a process speciﬁc part and embedded Flash Copyright 2019 2022 Arm Limited or its aﬃliates All rights reserved Non Conﬁdential Page 16 of 90 ...

Page 17: ...mory interface Flash power control eFlash macro Flash data path Flash power management Main system secondary domain AHB interconnect APB AHB Lite Secure enclave primary domain partition_ctrl_ro 15 0 Power Policy Unit Q Channel power ACG Address decoding AHB2APB bridge APB Arm TrustZone technology ﬁlters AHB and APB interconnects partition_ctrl_rd 15 0 partition_ctrl_rw 15 0 Clock controller ACG cl...

Page 18: ...if an access is not aligned Line buﬀers If the conﬁgured GFB data width is greater than the AHB data width then each domain has a dedicated line buﬀer in the AHB interface logic Each line buﬀer can store an entire Flash read data word If a new AHB read request targets an address for which the data is available in the line buﬀer then the GFC 200 fulﬁlls the request without initiating any GFB transa...

Page 19: ...rt hreadyout A delayed GFB transfer response because the embedded Flash is slow to respond The GFB arbiter block selects a diﬀerent requestor to access the memory An AHB manager initiates a transfer while a Q Channel interface is in the Q_STOPPED state The GFB has a transfer in progress A Flash write or erase operation can require millions of clock cycles that can signiﬁcantly block the AHB interc...

Page 20: ...ess speciﬁc part The MSB paddr_s 12 selects either internal or external accesses See 4 2 2 APB memory maps on page 38 for a description of the APB completer interface memory map Strobe signals The strobe signals are checked for writes to ensure that all bits are set to 1 to indicate 32 bit word accesses Otherwise the write is ignored and has no eﬀect on the registers The strobe signals are forward...

Page 21: ...B address region for the GFC 200 registers See 4 2 2 APB memory maps on page 38 for a description of the APB completer interface memory map Strobe signals For writes the GFC 200 requires that the strobe signal bits are all set to 1 to indicate a full 32 bit write If any pstrb_s1 bit is LOW the GFC 200 ignores the write so it has no eﬀect on the registers Delayed response Accesses to the internal r...

Page 22: ...mpleter delays an access is implementation dependent Error response Error responses that the GFC 200 APB requester interface receives are forwarded to the GFC 200 primary APB completer interface The conditions that determine when the attached APB completer responds with errors is implementation dependent Related information APB requester interface signals on page 85 3 2 5 GFB interface The Generic...

Page 23: ...or response For GFB transfers that fail the process speciﬁc part can generate a 2 cycle error response If the process speciﬁc part generates a 2 cycle error response the GFC 200 either Generates an AHB ERROR response when the transaction originates from an AHB manager Sets STATUS CMD_FAIL 1 when the transaction originates from an APB requester If a transfer fails then the eﬀect on the Flash macro ...

Page 24: ...erface signals on page 88 3 2 7 Q Channel interface for power The Q Channel interface for power is a control port for managing the system power The GFC 200 can accept or deny a request from an external Power Policy Unit PPU to turn oﬀ all operations that are using power Activity indication The GFC 200 uses the qactive_pwr signal to indicate when any ongoing activity requires power When GFC 200 ass...

Page 25: ...ate 4 0 signal to encode the various Flash macro power states See 3 7 Flash power control on page 30 for more information about the power states Responding to a request The GFC 200 initiates all activity and does not expect the process speciﬁc part to deny a request The time that the process speciﬁc part takes to accept a request depends on its implementation Related information P Channel controll...

Page 26: ...en the partition is accessible only for the domain owner and is inaccessible to the other domain If partition_ctrl_rd n is not equal to partition_ctrl_rw n then the partition is accessible for the domain owner and is read only to the other domain The GFC 200 samples the partition conﬁguration interface signals As it exits reset While it is in partition conﬁguration mode See 4 4 16 Partition conﬁgu...

Page 27: ...l controller sets the embedded Flash power to ON GFC 200 asserts the ﬂash_pwr_rdy signal This signal is sent to the process speciﬁc part GFB receiver so that it can initiate any startup sequence that requires the embedded Flash to be fully functional All the other interfaces operate without any restrictions The transfers from the AHB Lite subordinate interface are forwarded to the GFB but transfer...

Page 28: ...uts irq0 and irq1 The irq0 interrupt is for the primary domain and the irq1 interrupt is for the secondary domain There are multiple sources that can trigger an interrupt output event The following sources can trigger an interrupt output event Command accept CMD_ACCEPT_IRQ The GFC 200 sets CMD_ACCEPT_IRQ to 1 when the arbiter accepts a write command to the CTRL register After clearing the interrup...

Page 29: ...ter The IRQ_ENABLE_SET CMD_FAIL_IRQ_EN_SET bit controls whether the relevant irq signal goes HIGH when CMD_FAIL_IRQ is set to 1 Command reject CMD_REJECT_IRQ The GFC 200 sets CMD_REJECT_IRQ to 1 when software attempts to write to the CTRL ADDR or DATA0 registers either While a command is pending in the CTRL register When any GFB command related interrupts are pending The IRQ_ENABLE_SET CMD_REJECT_...

Page 30: ...PB completer interfaces and it forwards them to the Generic Flash Bus A simple grant request mechanism selects the appropriate interface Arbitration scheme The GFB arbiter uses a round robin arbitration scheme between the AHB Lite subordinate interface and the two APB completer interfaces When the AHB Lite subordinate interface sends a burst or locked transfer the AHB Lite subordinate interface ha...

Page 31: ...sters control the chosen PPU power mode The following table shows the mapping of the PSTATE values to the PPU power modes and the Flash power modes Table 3 1 PSTATE to PPU and Flash power modes PSTATE 4 0 PPU power mode Flash power mode 0b1_1000 ON OPMODE_1 All powerup low voltage read mode 0b0_1000 ON OPMODE_0 All powerup 0b1_0111 FUNC_RET OPMODE_1 Sleep low voltage read mode 0b0_0111 FUNC_RET OP...

Page 32: ... locations Attempting to access these locations can result in unpredictable behavior Unless otherwise stated in the accompanying text Do not modify undeﬁned register bits Ignore undeﬁned register bits on reads All register bits are reset to the reset value speciﬁed in the 4 3 Register summary on page 39 Access type is described as follows RW Read and write RO Read only WO Write only 4 2 Memory map...

Page 33: ...ry Extended area Main area Extension page 0 Extension page 1 Reserved Page 0 Page 1 Page 255 Read Read Read Write Read Write Memory mapped access Register based access AHB Lite APB0 APB1 System address 0xFFFF_FFFF GFC 200 register base 0x0000_2000 GFC 200 register base GFC 200 memory base 0x0040_0000 GFC 200 memory base 0x0000_0000 0x0000_0000 0x0000_1000 0x0000_2000 0x0010_0000 0x0020_0000 0x0020...

Page 34: ...artition control input signals control the accessibility of each partition in the memory map These quasi static inputs control whether the primary domain or secondary domain is the owner of a partition and also the access rights that the domains are granted Therefore the partition control input signals aﬀect the accessibility of the memory map See 3 2 9 Partition conﬁguration interface on page 25 ...

Page 35: ...s blocked The process specific part must prevent aliasing and must not map the same addresses multiple times within the 4MB address space of the Flash area For any out of range addresses Arm expects the process specific part to respond with error The primary domain can access the ﬁrst 128 pages only using either AHB hpart set LOW during address phase and APB 0 The secondary domain can access pages...

Page 36: ... PAGE 128 PAGE 254 PAGE 255 EXT PAGE 0 EXT PAGE 1 READ WRITE READ WRITE READ WRITE Access violation hpart is HIGH hpart is LOW hpart is HIGH hpart is LOW hpart is HIGH hpart is LOW READ Legend Primary domain Secondary domain Access granted Access blocked These blank regions are assigned to a domain but for this example the actual assignment is not relevant The process specific part must prevent al...

Page 37: ... 254 PAGE 255 EXT PAGE 0 EXT PAGE 1 READ WRITE READ WRITE READ Access violation hpart is HIGH hpart is LOW hpart is HIGH hpart is LOW hpart is HIGH hpart is LOW READ Legend Primary domain Secondary domain Access granted Access blocked These blank regions are assigned to a domain but for this example the actual assignment is not relevant READ The process specific part must prevent aliasing and must...

Page 38: ...her memory GFC 200 registers Other memory Primary domain APB 0 memory map Secondary domain APB 1 memory map Secondary domain GFC 200 register base 0x1000 Primary domain GFC 200 register base Primary domain GFC 200 register base 0x1000 Primary domain GFC 200 register base 0x2000 Each APB interface has a separate 4KB register space that enables an APB domain requester to program the GFC 200 function...

Page 39: ...4 7 Status register STATUS on page 49 0x01C ADDR RW 0x0 4 4 8 Address register ADDR on page 50 0x020 DATA0 RW 0x0 4 4 9 Data 0 register DATA0 on page 51 0x024 DATA1 RO 0x0 4 4 10 Data 1 register DATA1 on page 52 0x028 DATA2 RO 0x0 4 4 11 Data 2 register DATA2 on page 53 0x02C DATA3 RO 0x0 A banked register that is unique to each APB interface 4 4 12 Data 3 register DATA3 on page 54 0x030 PART_CTRL...

Page 40: ...age 67 0xFE8 PIDR2 RO 0x0B 4 4 26 Peripheral ID register 2 PIDR2 on page 68 0xFEC PIDR3 RO 0x00 4 4 27 Peripheral ID register 3 PIDR3 on page 69 0xFF0 CIDR0 RO 0x0D 4 4 28 Component ID register 0 CIDR0 on page 70 0xFF4 CIDR1 RO 0xF0 4 4 29 Component ID register 1 CIDR1 on page 71 0xFF8 CIDR2 RO 0x05 4 4 30 Component ID register 2 CIDR2 on page 72 0xFFC CIDR3 RO 0xB1 A shared register for both APB ...

Page 41: ...pts on the irq0 signal For the secondary requester this bit is reserved and behaves RAZ WI 6 PART_CONFIG_MODE_IRQ_EN_SET Set to 1 to enable the PART_CONFIG_MODE_IRQ bit to generate interrupts on the irq0 signal For the secondary requester this bit is reserved and behaves RAZ WI 5 PWR_STATE_CHANGE_IRQ_EN_SET Set to 1 to enable the PWR_STATE_CHANGE_IRQ bit to generate interrupts on the interrupt sig...

Page 42: ...t generate an interrupt to the APB requester The IRQ_ENABLE_CLR register characteristics are Usage constraints Setting a bit to zero has no eﬀect Bits 7 6 functionality is accessible to the primary requester only Conﬁgurations Available in all conﬁgurations Each APB interface has its own instance of an IRQ_ENABLE_CLR register Attributes Oﬀset 0x004 Type Read write Reset 0x0 Width 32 The following ...

Page 43: ...o 1 to disable the CMD_FAIL_IRQ bit from generating interrupts on the interrupt signal irq0 or irq1 that belongs to the APB requester 1 CMD_SUCCESS_IRQ_EN_CLR Set to 1 to disable the CMD_SUCCESS_IRQ bit from generating interrupts on the interrupt signal irq0 or irq1 that belongs to the APB requester 0 CMD_ACCEPT_IRQ_EN_CLR Set to 1 to disable the CMD_ACCEPT_IRQ bit from generating interrupts on th...

Page 44: ...G_MODE_IRQ_STS_SET Set to 1 to set the PART_CONFIG_MODE_IRQ bit to 1 For the secondary requester this bit is reserved and behaves as RAZ WI 5 PWR_STATE_CHG_IRQ_STS_SET Set to 1 to set the PWR_STATE_CHANGE_IRQ bit to 1 4 READ_OVERFLOW_IRQ_STS_SET Set to 1 to set the READ_OVERFLOW_IRQ bit to 1 3 CMD_REJECT_IRQ_STS_SET Set to 1 to set the CMD_REJECT_IRQ bit to 1 2 CMD_FAIL_IRQ_STS_SET Set to 1 to set...

Page 45: ...ts own instance of an IRQ_STATUS_CLR register Attributes Oﬀset 0x00C Type Read write Reset 0x0 Width 32 The following ﬁgure shows the bit assignments Figure 4 9 IRQ_STATUS_CLR register bit assignments 31 8 7 6 5 4 3 2 1 0 Reserved ACC_VIOLATION_IRQ_STS_CLR CMD_ACCEPT_IRQ_STS_CLR CMD_SUCCESS_IRQ_STS_CLR CMD_FAIL_IRQ_STS_CLR CMD_REJECT_IRQ_STS_CLR READ_OVERFLOW_IRQ_STS_CLR PART_CONFIG_MODE_IRQ_STS_C...

Page 46: ...its The IRQ_MASKED_STATUS also provides the status of the interrupt bits However the values that IRQ_MASKED_STATUS returns might diﬀer from the IRQ_STATUS_CLR value because the IRQ_MASKED_STATUS value depends on whether an interrupt is enabled 4 4 5 Interrupt masked status register IRQ_MASKED_STATUS The IRQ_MASKED_STATUS register shows the status of the interrupt bits The value that it returns dep...

Page 47: ...ANGE_IRQ is the cause of the interrupt assertion 4 READ_OVERFLOW_IRQ If this bit returns 1 the READ_OVERFLOW_IRQ is the cause of the interrupt assertion 3 CMD_REJECT_IRQ If this bit returns 1 the CMD_REJECT_IRQ is the cause of the interrupt assertion 2 CMD_FAIL_IRQ If this bit returns 1 the CMD_FAIL_IRQ is the cause of the interrupt assertion 1 CMD_SUCCESS_IRQ If this bit returns 1 the CMD_SUCCESS...

Page 48: ...SE commands When ABORT is set to 1 the GFC 200 ignores the CMD ﬁeld Reading the ABORT bit shows whether the APB requester has requested an abort for the ongoing command 3 Reserved 2 0 CMD Initiates a command to the embedded Flash using the address in the ADDR register and the data in the DATA0 register The commands are 0b001 READ 0b010 WRITE Software must ensure that the addressed region in Flash ...

Page 49: ...age constraints Conﬁgurations Available in all conﬁgurations Each APB interface has its own instance of a STATUS register Attributes Oﬀset 0x018 Type Read only Reset 0x0 Width 32 The following ﬁgure shows the bit assignments Figure 4 12 STATUS register bit assignments 31 6 5 4 3 2 1 0 Reserved CMD_SUCCESS CMD_ACCEPT CMD_PENDING CMD_FAIL CMD_FINISH ARBITRATION_LOCKED The following table shows the r...

Page 50: ... 0 when software sets IRQ_STATUS_CLR CMD_SUCCESS_IRQ_STS_CLR 1 which clears the CMD_SUCCESS_IRQ bit 1 CMD_ACCEPT When this bit returns 1 it indicates that the embedded Flash accepted the command The GFC 200 clears this bit to 0 when software clears the CMD_SUCCESS_IRQ or CMD_FAIL_IRQ status bits by writing to the IRQ_STATUS_CLR register However if the GFC 200 receives a command before software cle...

Page 51: ...d The following table shows the register bit assignments Table 4 9 ADDR Bits Name Function 31 22 Reserved 21 0 ADDR The address for the current Flash access 4 4 9 Data 0 register DATA0 The DATA0 register contains data bits 31 0 for a read or write access to the embedded Flash The DATA0 register characteristics are Usage constraints There are no usage constraints Conﬁgurations Available in all conﬁ...

Page 52: ...0 For writes to the embedded Flash this ﬁeld contains the write data bits 31 0 4 4 10 Data 1 register DATA1 The DATA1 register contains data bits 63 32 for a read or write access to the embedded Flash The DATA1 register characteristics are Usage constraints There are no usage constraints Conﬁgurations Available in conﬁgurations where FWDATA_WIDTH 32 When present each APB interface has its own inst...

Page 53: ...Data 2 register DATA2 The DATA2 register contains data bits 95 63 for a read or write access to the embedded Flash The DATA2 register characteristics are Usage constraints There are no usage constraints Conﬁgurations Available in conﬁgurations where FWDATA_WIDTH 64 When present each APB interface has its own instance of a DATA2 register Attributes Oﬀset 0x028 Type Read write Reset 0x0 Width 32 The...

Page 54: ...age constraints There are no usage constraints Conﬁgurations Available in conﬁgurations where FWDATA_WIDTH 64 When present each APB interface has its own instance of a DATA3 register Attributes Oﬀset 0x02C Type Read write Reset 0x0 Width 32 The following ﬁgure shows the bit assignments Figure 4 17 DATA3 register bit assignments 31 0 DATA3 The following table shows the register bit assignments Tabl...

Page 55: ...nal when it exits reset and while it is in partition conﬁguration mode Width 32 The following ﬁgure shows the bit assignments Figure 4 18 PART_CTRL_RW_STATUS register bit assignments 31 16 15 0 PART_CTRL_RW_STATUS Reserved The following table shows the register bit assignments Table 4 14 PART_CTRL_RW_STATUS Bits Name Function 31 16 Reserved 15 0 PART_CTRL_RW_STATUS Each bit indicates which domain ...

Page 56: ...e of the partition_ctrl_ro 15 0 signal The GFC 200 reads this signal when it exits reset and while it is in partition conﬁguration mode Width 32 The following ﬁgure shows the bit assignments Figure 4 19 PART_CTRL_RO_STATUS register bit assignments 31 16 15 0 PART_CTRL_RO_STATUS Reserved The following table shows the register bit assignments Table 4 15 PART_CTRL_RO_STATUS Bits Name Function 31 16 R...

Page 57: ...s signal when it exits reset and while it is in partition conﬁguration mode Width 32 The following ﬁgure shows the bit assignments Figure 4 20 PART_CTRL_RD_STATUS register bit assignments 31 16 15 0 PART_CTRL_RD_STATUS Reserved The following table shows the register bit assignments Table 4 16 PART_CTRL_RD_STATUS Bits Name Function 31 16 Reserved 15 0 PART_CTRL_RD_STATUS Each bit indicates if the s...

Page 58: ...ister space only Attributes Oﬀset 0x040 Type Read write Reset 0x0 Width 32 The following ﬁgure shows the bit assignments Figure 4 21 PART_CONFIG_MODE_REQ register bit assignments 31 1 0 Reserved PART_CONFIG_MODE_REQ The following table shows the register bit assignments Table 4 17 PART_CONFIG_MODE_REQ Bits Name Function 31 1 Reserved 0 PART_CONFIG_MODE_REQ Set to 1 to request that the GFC 200 ente...

Page 59: ...teristics are Usage constraints Accessible to the primary APB requester only Conﬁgurations Available in all conﬁgurations This register is present in the primary APB interface register space only Attributes Oﬀset 0x044 Type Read only Reset 0x0 Width 32 The following ﬁgure shows the bit assignments Figure 4 22 PART_CONFIG_MODE_STATUS register bit assignments 31 1 0 Reserved PART_CONFIG_MODE_STATUS ...

Page 60: ...WI if the primary domain performs an access violation The ACCESS_ERR_RESP_CTRL register characteristics are Usage constraints Accessible to the primary APB requester only Conﬁgurations Available in all conﬁgurations This register is present in the primary APB interface register space only Attributes Oﬀset 0x048 Type Read write Reset 0x0 Width 32 The following ﬁgure shows the bit assignments Figure...

Page 61: ...s all zeros Write access violation The GFC 200 ignores the write transfer Note If the secondary domain performs any access violation the GFC 200 always provides an error response 4 4 19 Access violation response register ACCESS_ERR_INFO The ACCESS_ERR_INFO register returns the embedded Flash address location for the most recent GFB access violation by either domain The ACCESS_ERR_INFO register cha...

Page 62: ...4 20 Power state status register POWER_STATE The POWER_STATE register returns the Flash macro power state and whether the Flash macro is in low voltage mode The POWER_STATE register characteristics are Usage constraints There are no usage constraints Conﬁgurations Available in all conﬁgurations Attributes Oﬀset 0x050 Type Read only Reset 0x8 Width 32 The following ﬁgure shows the bit assignments F...

Page 63: ...macro is fully powered on 4 4 21 Power state request register POWER_STATE_REQ The POWER_STATE_REQ register enables software to set its minimum required Flash macro power state and its minimum required Flash macro operating mode The POWER_STATE_REQ register characteristics are Usage constraints There are banked copies of this register between the two APB interfaces The GFC 200 compares the requirem...

Page 64: ...eld to set the minimum required Flash macro power 0b000 OFF The Flash macro can power oﬀ 0b001 PD The Flash macro can enter powerdown mode 0b01x SL The Flash macro can enter sleep mode 0b1xx ON The Flash macro must remain fully powered on Where x is a don t care value Related information Flash macro power control on page 81 4 4 22 Hardware parameters register HWPARAMS The HWPARAMS register returns...

Page 65: ...ssible values are 0x0F 16KB Flash partition size 0x1F 32KB Flash partition size 0x3F 64KB Flash partition size 0x7F 128KB Flash partition size 0xFF 256KB Flash partition size 23 Reserved returns 0 22 16 FWDATA_WIDTH Returns the value of FWDATA_WIDTH 1 The possible values are 0b0011111 32 bit GFB write data bus width 0b0111111 64 bit GFB write data bus width 0b1111111 128 bit GFB write data bus wid...

Page 66: ...ing system discovery can use the peripheral ID to discover which peripherals are in the system and the size of the programming register space The PIDR4 register characteristics are Usage constraints There are no usage constraints Conﬁgurations Available in all conﬁgurations Attributes Oﬀset 0xFD0 Type Read only Reset 0x4 Width 32 The following ﬁgure shows the bit assignments Figure 4 28 PIDR4 regi...

Page 67: ...l identiﬁer A debugger during system discovery can use the peripheral ID to discover which peripherals are in the system The PIDR0 register characteristics are Usage constraints There are no usage constraints Conﬁgurations Available in all conﬁgurations Attributes Oﬀset 0xFE0 Type Read only Reset 0x33 Width 32 The following ﬁgure shows the bit assignments Figure 4 29 PIDR0 register bit assignments...

Page 68: ...rations Attributes Oﬀset 0xFE4 Type Read only Reset 0xB8 Width 32 The following ﬁgure shows the bit assignments Figure 4 30 PIDR1 register bit assignments 31 8 7 4 3 0 PART_1 DES_0 Reserved The following table shows the register bit assignments Table 4 26 PIDR1 Bits Name Function 31 8 Reserved returns 0 7 4 DES_0 The JEDEC JEP106 ID code 3 0 which identiﬁes Arm as the designer of the GFC 200 See a...

Page 69: ...s Attributes Oﬀset 0xFE8 Type Read only Reset 0x0B Width 32 The following ﬁgure shows the bit assignments Figure 4 31 PIDR2 register bit assignments 31 8 7 4 3 2 0 DES_1 REVISION Reserved JEDEC The following table shows the register bit assignments Table 4 27 PIDR2 Bits Name Function 31 8 Reserved returns 0 7 4 REVISION Revision identiﬁer for the GFC 200 0x0 r0p0 3 JEDEC Returns 1 which indicates ...

Page 70: ... Attributes Oﬀset 0xFEC Type Read only Reset 0x00 Width 32 The following ﬁgure shows the bit assignments Figure 4 32 PIDR3 register bit assignments 31 Reserved 0 4 3 8 7 CMOD REVAND The following table shows the register bit assignments Table 4 28 PIDR3 Bits Name Function 31 8 Reserved returns 0 7 4 REVAND A nonzero value indicates that Arm has approved the application of a post manufacture metal ...

Page 71: ... 0x0D Width 32 The following ﬁgure shows the bit assignments Figure 4 33 CIDR0 register bit assignments 31 8 7 0 PRMBL_0 Reserved The following table shows the register bit assignments Table 4 29 CIDR0 Bits Name Function 31 8 Reserved returns 0 7 0 PRMBL_0 Preamble 0 Returns segment 1 of the component identiﬁcation code 4 4 29 Component ID register 1 CIDR1 The CIDR1 register returns byte 1 of the ...

Page 72: ...DR1 Bits Name Function 31 8 Reserved returns 0 7 4 CLASS Component class Returns 0xF which indicates that the GFC 200 belongs to the CoreLink family 3 0 PRMBL_1 Preamble 1 Returns segment 2 of the component identiﬁcation code 4 4 30 Component ID register 2 CIDR2 The CIDR2 register returns byte 2 of the component ID A debugger during system discovery can use the component ID to discover that the pe...

Page 73: ...on 31 8 Reserved returns 0 7 0 PRMBL_2 Preamble 2 Returns segment 2 of the component identiﬁcation code 4 4 31 Component ID register 3 CIDR3 The CIDR3 register returns byte 3 of the component ID A debugger during system discovery can use the component ID to discover that the peripheral contains a programmers register block The CIDR3 register characteristics are Usage constraints There are no usage...

Page 74: ...ster bit assignments Table 4 32 CIDR3 Bits Name Function 31 8 Reserved returns 0 7 0 PRMBL_3 Preamble 3 Returns segment 3 of the component identiﬁcation code 4 5 Accessing Flash from the APB completer interfaces Software must follow a particular ﬂow to access the embedded Flash from the APB completer interfaces The following ﬁgure shows how to access the embedded Flash from an APB completer interf...

Page 75: ...TA registers for READ commands Clear IRQ_STATUS register Write ADDR register Write command Write CTRL register Write DATA register No Yes No Yes Yes Polling method Interrupt method The APB completer interface can use either of two modes to trigger a new command Polling method Software polls the STATUS register for any active bits where an active bit indicates that GFC 200 is processing a command C...

Page 76: ... reading the IRQ_STATUS _SET or IRQ_STATUS_CLR register If these conditions are not met the GFC 200 ignores the write to the CTRL ADDR or DATA0 registers and sets CMD_REJECT_IRQ 1 to indicate a programming fault This behavior ensures that software does not change the value of a pending command on the GFB interface and forces software to process the result of the previously executed transaction Rel...

Page 77: ...ady to immediately accept the command at t2 and the command then passes to the GFB After t2 the GFC 200 clears the CTRL register automatically and asserts the CMD_ACCEPT_IRQ interrupt Wait IRQ Software waits until it receives the interrupt Serve IRQ Software acknowledges the interrupt by writing to the IRQ_STATUS_CLR register When the IRQ_STATUS register clears the address and data for the next tr...

Page 78: ...er Technical Reference Manual Document ID 101484_0000_01_en Issue 01 Programmers Model The following ﬁgure shows the ROW WRITE preloading ﬂowchart Copyright 2019 2022 Arm Limited or its aﬃliates All rights reserved Non Conﬁdential Page 78 of 90 ...

Page 79: ...TRL register Wait CMD_ACCEPT_IRQ Read IRQ_STATUS Last command sent Write ADDR register Write DATA register Write CTRL register No CMD_SUCCESS_IRQ or CMD_FAIL_IRQ set No Clear CMD_ACCEPT_IRQ status This writes address n ROW WRITE finished Clear CMD_SUCCESS_IRQ or CMD_FAIL_IRQ Wait CMD_SUCCESS_IRQ or CMD_FAIL_IRQ Clear CMD_SUCCESS_IRQ or CMD_FAIL_IRQ This is the status of the command for address n 1...

Page 80: ... use this feature for ROM emulation when software locks down a memory region to be read only accessible During partition reconﬁguration software must ensure that any sensitive data is not compromised Example 4 4 Example ﬁrmware update process During a ﬁrmware update software must perform the following steps 1 The primary and secondary domains negotiate with each other to enter a secure maintenance...

Page 81: ...on mode after it completes any pending GFB command 8 Software instructs the primary and secondary managers to exit from the secure maintenance update mode Related information Partition conﬁguration mode request register PART_CONFIG_MODE_REQ on page 57 4 8 Flash macro power control Each domain programs the POWER_STATE_REQ register with their minimum power state that they require for the Flash macro...

Page 82: ...his signal and only initiate transactions towards the Flash macro when ﬂash_pwr_rdy is HIGH ﬂash_pwr_opmode Output Indicates the Flash power operating mode to the GFB receiver logic 0 The Flash is in OPMODE_0 operational mode default 1 The Flash is in OPMODE_1 operational mode ﬂash_devisolaten Output Active LOW isolation control output This signal controls isolation cells that isolate the Flash ma...

Page 83: ...icates whether the transfer on the bus is atomic Used for blocking arbitration over the GFB hready Input When HIGH indicates that a bus transfer has completed hpart Input Domain identiﬁer hpart indicates which domain the transfer originates from 0b0 Primary domain 0b1 Secondary domain hpart must be driven during the address phase of each AHB transfer and also remain stable during waited transfers ...

Page 84: ...peciﬁc part pstrb_s0 3 0 Input Write strobe port Each bit refers to a byte in the pwdata_s0 signal pwrite_s0 Input APB transfer direction pwdata_s0 31 0 Input 32 bit write data bus pwakeup_s0 Input The APB bridge sets this signal HIGH when a transfer is in progress on the primary APB interface APB 0 prdata_s0 31 0 Output 32 bit read data bus Reset value 0x0 pready_s0 Output Driven LOW when extra w...

Page 85: ...200 to access the registers in the process speciﬁc part The following table shows the signals that are used by the APB requester interface Table A 5 APB requester interface signals Signal name Direction Description psel_m Output Process speciﬁc part select signal penable_m Output Indicates the start of the second cycle of an APB transfer paddr_m 11 0 Output Address bus pstrb_m 3 0 Output Write str...

Page 86: ...th is 32 bits fcmd 2 0 Output Command bus 0b000 IDLE 0b001 READ 0b010 WRITE 0b011 ROW WRITE 0b100 ERASE 0b101 Reserved 0b110 Reserved 0b111 MASS ERASE fabort Output Abort indication When HIGH the manager requests to abort the command that is running fwdata FWDATA_WIDTH 1 0 Output Write data bus frdata FRDATA_WIDTH 1 0 Input Read data bus fready Input Command ready indication Driven LOW if the proc...

Page 87: ...ding partition in the Flash Bit n 0 The primary domain is the owner of partition n Bit n 1 The secondary domain is the owner of partition n The owner of a partition has read and write access to it unless partition_ctrl_ro sets the partition as read only When 16 PARTITION_SIZE is smaller than the address space of the Flash the last control input sets the state of the remaining part of the Flash Whe...

Page 88: ... indicates when the clock controller issues a quiescence entry or exit request to the GFC 200 The input contains a 2 stage synchronizer so the signal can transition asynchronously clk_qacceptn This signal indicates when the GFC 200 accepts the quiescence request clk_qdeny This signal indicates when the GFC 200 denies the quiescence request clk_qactive Output This signal indicates when the GFC 200 ...

Page 89: ...ication Active HIGH Synchronized with double ﬂop synchronizer The GFC 200 does not provide the pdeny and pactive input signals Therefore the process speciﬁc part cannot deny a power state transition nor can it request a certain power state Related information P Channel controller interface on page 25 A 9 DFT signals The GFC 200 provides Design for Test DFT signals A DFT controller controls these s...

Page 90: ... released issues of this book Table B 1 Issue 0000 00 Change Location Aﬀects First release Table B 2 Diﬀerences between issue 0000 00 and issue 0000 01 Change Location Aﬀects Removed oﬀensive terms Added inclusive language statement Throughout document Inclusive language commitment on page 4 All versions Copyright 2019 2022 Arm Limited or its aﬃliates All rights reserved Non Conﬁdential Page 90 of...

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