Arm
®
CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Programmers Model
Table 4-21: POWER_STATE
Bits
Name
Function
[31:4]
-
Reserved.
[3]
NON_LV_MODE
This bit indicates whether the Flash macro is in low-voltage mode:
0 == The Flash macro is in low-voltage mode.
1 == The Flash macro is on and is not in low-voltage mode.
[2:0]
POWER_STATE
This field indicates the current Flash macro power state:
0b000
== OFF. The Flash macro is powered off.
0b001
== PD. The Flash macro is in powerdown mode.
0b010
== SL. The Flash macro is in sleep mode.
0b100
== ON. The Flash macro is fully powered on.
4.4.21 Power state request register, POWER_STATE_REQ
The POWER_STATE_REQ register enables software to set its minimum required Flash macro power
state and its minimum required Flash macro operating mode.
The POWER_STATE_REQ register characteristics are:
Usage constraints
There are banked copies of this register between the two APB interfaces. The GFC-200
compares the requirements from both APB interfaces and selects the higher requirements.
Configurations
Available in all configurations. Each APB interface has its own instance of a
POWER_STATE_REQ register.
Attributes
Offset
0x054
Type
Read/write.
Reset
0x8
.
Width
32
The following figure shows the bit assignments.
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