ARM ARM9TDMI, Technical Reference Manual

Page: 114 / 154

Instruction Cycle Summary and Interlocks
7-4 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
Table 7-3 shows the instruction cycle times from the perspective of the data bus:
7.1.1 Multiplier cycle counts
The number of cycles that a multiply instruction takes to complete depends on which
instruction it is, and on the value of the multiplier-operand. The multiplier-operand is
the contents of the register specified by bits [8:11] of the ARM multiply instructions, or
bits [2:0] of the Thumb multiply instructions.
• For ARM MUL, MLA, SMULL, SMLAL, and Thumb MUL, m is:
1 if bits [31:8] of the multiplier operand are all zero or one
2 if bits [31:16] of the multiplier operand are all zero or one
3 if bits [31:24] of the multiplier operand are all zero or all one
4 otherwise.
• For ARM UMULL, UMLAL, m is:
1 if bits [31:8] of the multiplier operand are all zero
2 if bits [31:16] of the multiplier operand are all zero
3 if bits [31:24] of the multiplier operand are all zero
4 otherwise.
Table 7-3 Data bus instruction times
Instruction Cycle time
LDR 1N
STR 1N
LDM,STM 1N+(n-1)S
SWP 1N+1S
LDC, STC 1N+(n-1)S
MCR,MRC 1C