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Operation
PCI Bus Interface
The PCI bus is a high speed alternative to ISA bus, it has been designed to overcome some of the
limitations of ISA bus, and provide faster throughput for I/O intensive peripheral devices. PCI bus
also supports Plug and Play configuration which allows the system software to allocate resources
during initialisation helping to overcome resource conflicts, which might exist in a system.
The APCI-SER4 uses a single chip PCI bus slave controller which is designed and manufactured by
PLX Technology. This device has been designed to fully support the PCI 2.1 specification and
provides plug and play software capabilities. During power-up initialisation the PCI BIOS will detect
the card and assign a unique I/O address location and interrupt line. This ensures that there are no
resource conflicts on the PCI bus. Multiple cards are supported through this mechanism without the
need for address decode links.
The PLX device contains a standard type 00H configuration space header. The table below shows the
registers within this header which are required for configuration of the APCI-SER4.
Configuration Space Header
These registers can be accessed using PCI BIOS functions. Please contact Arcoms customer support
team (Tel: 01223 412428) for a copy of the PCI BIOS Specification if required.
Enhanced Serial Communication Controllers
The APCI-SER4 contains two 85230 Enhanced Serial Communication Controllers (ESCC), each device
provides two full-duplex communication channels. The serial interface lines from these devices are
buffered on board by RS232 and RS485/422 devices.
The ESCC is a versatile and powerful device and requires careful initialisation. For this reason it is
recommended that the ESCC manufacturers manual is used. This may be obtained by contacting
Arcoms customer support team (Tel:01223 412428). It should be noted that these devices are
NOT
compatible with the PC 8250-type UART.
The order in which registers are initialised is important and a register may need to be accessed more
than once during initialisation. Unreliable operation may be experienced if short cuts are taken. For
examples of basic ESCC initialisation, please refer to the programs on the utility disk.
Each ESCC occupies four I/O locations in the APCI-SER4 indexed I/O map; two consecutive locations
per channel. The lower address of each pair is used to select the appropriate register within the
device, and to read/write data to the register. The higher address provides direct connection to the
receive and transmit data latches.
The internal ESCC registers are accessed using an indexed addressing scheme like the APCI-SER4.
The appropriate index must be written each time a register is accessed. Therefore each read/write
operation to a register must be preceded with a write to the index register. After a read/write
operation the index is reset to 0.
2192-09100-000-000
J592 APCI-SER4
Offset
00-01H
02-03H
18-1BH
2C-2DH
2E-2FH
3CH
Register Name
Vendor ID
Device ID
Base Address Register
Subsystem Vendor ID
Subsystem ID
Interrupt Line
Description
ID of PCI device manufacturer
ID of PCI device
ID of board manufacturer
ID of Board
Interrupt line assigned to device
I/O base address assigned to card
Value
10B5H (PLX Technology)
9050H
0000xxxx
13ABH (ARCOM)
0592H (APCI-SER4)
0x
