This PCB selects on of 8 external digital inputs or one of two internal digital
inputs & generates BClk, WClk & MClk for the DSP (see L156) & DAC (see
L117). It also generates the clocks for the ADC (see L116) when the unit is in
ADC mode.
The CD, AV & DVD inputs use coaxial connector SKT100 and feed into IC200
& IC201 (DS9637ACM buffers). The Tape, SAT, VCR & PVR inputs use
optical connectors RX100, RX101, RX102, RX103. The outputs are padded
down to give 3v3 outputs. There is also the Aux input which can be selected
(see L117), the Net input (see L119) and the HDMI SPDIF (see L122).
One of these inputs is then selected using IC202 & IC203 (74HC151 8-1 mux)
under the control of IC204 (74HC595D serial to parallel converter) controlled
by AN SPI Clk, AN SPI Data & Dig Mux Latch.
The selected input is fed to IC100 (WM8805 SPDIF Rx/Tx) which is controlled
from the PW338 via AN SCL, AN SDA & SPDIF /RESET. IC100 generates
8805MClk, 8805BClk & 8805WClk. Also, SPDIF Out which is a de-jittered
SPDIF stream which is then buffered by IC103 part A, B, C & D (parts E & F
are unused) to give both the optical output (TXC100) & 75ohmcoaxial output
(SKT101).
The selected input is also fed to IC205 part A (74HC123D monostable, part B
unused) which gives a high output from pin 13 (SPDIF_PRESENT to the
PW338) if an SPDIF signal is present.
BClk=64* WClk
MClk=128*WClk (192kHz/176.4kHz), 256*WClk (96kHz/88.2kHz), 512*WClk
(48kHz/44.1kHz) – this clock is used by the PSU to synchronise the switchers.
IC105 (XC95C36 Xilinx) generates a pre-delayed SPDIF stream from the
HDMI clocks (only MClk & WClk used) as the HDMI SPDIF is turned off
during HD audio transfer & the WM8805 does not have a zero delay PLL.
IC104 (74HCT157 Quad 2-1 mux) can also be used to re-direct the clocks
from the HDMI into the system.
IC100 (WM8805) can also operate in master mode to generate clocks for the
ADC when processing an analogue input.
3V3D is generated locally on the PCB from 5V_1 using REG200 (LM1117).
L115AY Digital Input – Output board