Industrial micro IDE Flash (MIF) Module - HERMIT Series © 2010 APRO Co., Ltd.
14
Multiword DMA
Figure 12: Read/Write Timing Diagram, Multiword DMA Mode
Table 15: Read/Write Timing Specifications, Multiword DMA Mode 0-2
Multiword DMA timing parameters
Mode 0
Mode 1
Mode 2
t
0
Cycle time (min.)
480
150
120
t
D
HIOR-/HIOW- assertion width (min.)
215
80
70
t
E
HIOR- data access (max.)
150
60
50
t
F
HIOR- data hold (min.)
5
5
5
t
G
HIOR-/HIOW- data setup (min.)
100
30
20
t
H
HIOW- data hold (min.)
20
15
10
t
I
DMACK to HIOR-/HIOW- setup (min.)
0
0
0
t
J
HIOR-/HIOW- to DMACK hold (min.)
20
5
5
t
KR
HIOR- negated width (min.)
50
50
25
t
KW
HIOW- negated width (min.)
215
50
25
t
LR
HIOR- to DMARQ delay (max.)
120
40
35
t
LW
HIOW- to DMARQ delay (max.)
40
40
35
t
M
CS1-, CS0- valid to HIOR-/HIOW-
50
30
25
t
N
CS1-, CS0- hold
15
10
10
t
Z
DMACK-
20
25
25
