AOC TCL LCD27VN, Service Manual, Page: 41 / 74

27
’’ LCD TV Color Monitor TCL LCD27VN
41
+1.8V _CORE
B L UE + 7
RE D- 7
A UDI O_ M UT E 1 1
DA T 1 0
C4 4 4
0 .1 u F/ 1 6 V
+3.3V _I/O_B GA
Ri n 3 - 1 0
RX D 7
/F S B KS E L U1
OCM ADDR5
/F S DAT A U8
C4 2 9
0 .1 u F/ 1 6 V
+
C4 5 2
2 2 u F /1 6 V
C4 2 3
0 .1 u F/ 1 6 V
F S DA T A 9
M S T R_ S DA
R4 1 1
1 0 K£ [ 1 /1 6 W
Ri n 2 - 1 0
/F S DAT A U2
T X A2 +
/F S DQS U
U4 0 4 B
7 4 L V C1 4
3 4
14
7
R4 2 6
1 0 K£ [ 1 /1 6 W
To 3D Comb_filter RSTB
RCL K - 1 0
/FSRAS 9
D4 0 2
L E D
C4 7 5
3 3 p F
F S DA T A 1 5
/F S A DDRU6
Q4 0 1
P M B S3 9 0 4
3
2
1
Q4 0 8
P M B S3 9 0 4
3
2
1
C4 3 8
0 .1 u F/ 1 6 V
From AD9883 DataCLK
Back_light Adj
+5V P
+12V
F S DA T A [0 .. 3 1 ]
T X A0 -
A DC_ G6
F S ADDR3
F S ADDR8
R4 3 2
4 .7 K £ [ 1 /1 6 W
CN5 0 1
RE SE T
1
2
T 4 5 NC
C4 3 9
0 .1 u F/ 1 6 V
Unloaded trace impedance on this interface is 90 Ohm
Loaded trace impedace with DRAM load is 65 Ohm (for 2.5 inch total trace
length)
S OG 7
A UDI O_ S L 3 1 1
F S DA T A 2 8
/F S DAT A U1 7
S V DA T A 3
R4 4 9 NC
U4 0 4 A
7 4 L V C1 4
1 2
14
7
S CAL E R_ A V S 7
/OCM _ CS1
S V DA T A 7
C4 8 7
0 .1 u F/ 1 6 V
F S RA S
P R4 1 0 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
/F S DAT A U3 1
F S ADDR6
+
C5 0 8
1 0 u F /1 6 V
+3.3V _P LL
Ri n 0 + 1 0
/F S DAT A U2 9
OCM ADDR9
C4 6 3
0 .1 u F/ 1 6 V
R4 2 3
4 .7 K £ [ 1 /1 6 W
F S DA T A 1 7
OCM ADDR1
To E_frame
OCM ADDR7
OCM ADDR1 2
OCM ADDR2
F S DQM 1
S V DA T A 1
T X D
R4 2 8 NC
C4 3 0
0 .1 u F/ 1 6 V
Q4 0 6
P M B S3 9 0 4
3
2
1
/F S DAT A U7
R4 3 1
1 0 K£ [ 1 /1 6 W
F S VRE F
F S DA T A 1
OCM DA T A 4
A DC_ IN3
C5 0 2
0 .1 u F/ 1 6 V
C4 9 3
0 .1 u F/ 1 6 V
+ 3 .3 V_ A DC
OCMA DDR[0..19] 9
FSDQM [ 0. .3 ] 9
/F S DAT A U1 9
T 4 2 NC
R4 5 1
1 0 K£ [ 1 /1 6 W
C4 6 9
0 .1 u F/ 1 6 V
To 12V B+ Enable
F S DA T A 1 2
A DC_ G7
/F S DAT A U1 6
C5 1 3
0 .1 u F/ 1 6 V
+3.3V _I/O_B GA
+ 3 .3 V_ L V DSB
/F S A DDRU8
/F S DQM 1
A CS_ RS ET _ HD
/F S A DDRU9
R4 5 6
NC
C4 6 4
0 .1 u F/ 1 6 V
Route (VIN1/ADC_IN1, ADC1_RETURN) and (VIN2/ADC_IN2,
ADC2_RETURN) as differential tracks close to each other
and ground the return track of each pair very close to the
gm1601 D12 ball and ground pin
TO Flash ROM 29LV040B
+5V _P A NE L
F S DA T A 2 5
A DC_ R6
A DC_ IN1
C4 8 3
0 .1 u F
T 4 4 NC
Q4 0 3
P M B S3 9 0 6
3
2
1
C4 7 8
0 .1 u F
OCMD A TA [0..7] 9
OE XT R
P B IA S
T X A1 -
OCM DA T A 2
F S CL K U-
IR0
R4 3 0
1 0 K£ [ 1 /1 6 W
T 4 0 NC
C4 4 2
0 .1 u F/ 1 6 V
/FSWE 9
/F S DAT A U0
P W M 2
T X A0 +
+3.3V _P LL
INV E RT E R_ PROT ECT1 0
A UDI O_ S L 2 1 1
/F S DAT A U1
/F S DQM 3
P R4 0 8 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
Place Series termination resistors on all address and
control lines very close to gm1601 BGA
L 4 1 2
NC
F S DA T A 8
F S CL K +
+2.5V _DDR
/F S A DDRU5
/F S DAT A U2 1
C5 0 6
0 .1 u F/ 1 6 V
P R4 0 9 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
+1.8V _CORE
/F S DAT A U4
/F S A DDRU1 0
T 4 9 NC
+1.8V _A DC
S V DA T A 6
C4 2 8
0 .1 u F/ 1 6 V
C4 4 8
0 .1 u F/ 1 6 V
R4 2 5
4 .7 K £ [ 1 /1 6 W
From D_SUB
FS DA TA [0..31] 9
/F S DAT A U1 4
V 1_CLK 6,10
R4 3 3
4 .7 K £ [ 1 /1 6 W
FS A DDR [0..11] 9
/F S DAT A U2 4
C5 0 5
0 .1 u F/ 1 6 V
GREE N+ 7
A DC_ G1
/F S CKE
/F S DAT A U2 3
R4 2 0 1 K £ [ 1 /1 6 W
C4 6 6
0 .1 u F/ 1 6 V
C4 4 5
0 .1 u F/ 1 6 V
LED Control
A DC_R[0..7] 6,10
T 4 7 NC
GREE N- 7
/OCM _ RE 9
COM P_ S E L 6
/F S A DDRU3
P W M 1
+5V P
FSCKE 9
F S ADDR2
R4 3 4
1 0 K£ [ 1 /1 6 W
From 3230D Standard Video
P A NE L _ P
F S DA T A 1 4
OCM ADDR1 4
F S DQM 3
M S T R_ S DA
FS V RE F
F S DA T A 1 1
F S DA T A 5
/F S DAT A U1 1
C4 4 6
0 .1 u F/ 1 6 V
R4 1 9 1 K £ [ 1 /1 6 W
R4 0 8
3 .3 K £ [ 1 /1 6 W
+ 1 .8 V_ A DC
/F S RAS
C5 1 0
0 .1 u F/ 1 6 V
F S DA T A 2 4
+
C4 3 5
2 2 u F /1 6 V
C5 0 4
0 .1 u F/ 1 6 V
TO FRAME MEMORY MT46V2M32LG-4
+ 3 .3 V_ DIG
Ri n 0 - 1 0
TX D 7
/F S A DDRU1 1
+
C5 0 9
2 2 u F /1 6 V
T 4 8 NC
C4 2 4
0 .1 u F/ 1 6 V
Q4 0 4
P M B S3 9 0 4
3
2
1
C5 1 2
0 .1 u F/ 1 6 V
+3.3V _DIG
LE D_RE D 10
/F S DAT A U5
OCM ADDR6
R4 1 6
1 K £ [ 1 /1 6 W
+ 3 .3 V_ P L L
S CAL E R_ A HS 7
F S DA T A 2 1
T CL K
F S BK S E L 1
S V ODD
P R4 1 5 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
R4 1 7
1 0 K£ [ 1 /1 6 W
P R4 1 7 3 3 £ [ 1 /1 6 W
1
2
3
4 8
7
6
5
I2C address: A2H and A3H
LE D_GRN 10
S V DA TA [0..7] 4
A DC_ R1
OCM ADDR1 3
R4 5 4
4 .7 K £ [ 1 /1 6 W
C4 7 2
0 .1 u F/ 1 6 V
R4 2 9
1 0 K£ [ 1 /1 6 W
Optional Filter Caps in between a pair on LBADC differential tracks close
to the Malibu chip
TO LVDS Panal
/OCM _ W E
F S ADDR1 1
U403
GM1501
P B GA -4 1 6
A 2 0
B 2 0
C2 0
D1 9
D2 0
A F 1 7
A D1 6
A C1 6
A C1 7
A C7
Y 2 6
Y 2 5
W 2 6
V 2 4
V 2 6
V 2 5
T 2 5
A D4
A F 3
A E 3
A D3
A F 2
A E 2
A D2
A F 1
A E 1
A D1
A C1
A C2
A C3
A B 1
A B 2
A B 3
A A 1
A A 2
A A 3
Y 1
Y 2
Y 3
W 1
W 2
W 3
V 1
V 2
V 3
V 4
U1
U2
U3
U4
T 1
T 2
T 3
T 4
P 1
P 2
L 2
L 1
R1
R2
R3
K 1
L 4
L 3
N2
N1
N4
N3
M 4
M 3
M 2
M 1
P 4
P 3
R4
A D2 5
A D2 6
A C2 4
A C2 5
A B 2 6
A A 2 4
A A 2 5
A A 2 6
A C2 6
A B 2 4
A B 2 5
Y 2 4
E 2 4
E 2 5
E 2 6
G2 6
G2 4
H2 6
H2 4
J 2 5
T 2 6
R2 5
P 2 4
P 2 6
N2 4
N2 6
M 2 5
L 2 4
L 2 5
M 2 6
M 2 4
N2 5
N2 3
P 2 5
R2 6
R2 4
K 2 4
J 2 6
H2 5
G2 3
G2 5
F 2 4
F 2 5
F 2 6
T 2 4
U2 6
U2 5
L 2 6
U2 4
U2 3
C1 6
B 1 6
A 1 6
D1 5
C1 5
B 1 5
A 1 5
D1 4
A 1 4
B 1 4
C1 4
D1 6
A 1 7
C1 9
B 1 9
A 1 9
D1 8
C1 8
B 1 8
A 1 8
C1 7
A 2 3
C2 2
B 2 2
A 2 2
D2 1
C2 1
B 2 1
A 2 1
B 2 5
A 2 5
D2 4
C2 4
B 2 4
A 2 4
C2 3
B 2 3
C2 6
C2 5
D2 6
D2 5
D5
C5
B 6
A 6
B 1 0
A 1 0
A 9
B 9
A 8
B 8
B 1 1
C1 2
B 1 2
A 1 2
A 1
B 1
B 2
C1
C2
D1
D2
C3
F 1
G3
G4
K 3
K 2
A C1 8
A D1 8
A E 1 8
A F 1 8
A E 1 9
A F 1 9
A E 2 0
A F 2 0
A D2 1
A E 2 1
A F 2 1
A D2 2
A E 2 2
A F 2 2
A E 2 3
A F 2 3
A D2 3
A D2 4
A E 2 4
A F 2 4
A F 2 5
A F 2 6
A E 2 5
A E 2 6
A D1 5
A D8
A F 7
A E 7
A F 6
A E 6
A D6
A F 5
A E 5
A D7
A D5
A C5
A F 4
A E 4
K
1
7
U
1
7
U
1
1
L16 T
1
6
T
1
7
L11 K
1
0
K
1
6
T
1
1
U
1
6
U
1
0
K
1
1
U
1
4
L15 M
1
5
P
1
5
R
1
5
U
1
5
M
1
1
N
1
1
R
1
1
P
1
6
N
1
7
N
1
0
R
1
0
K
1
2
L12 M
1
3
M
1
2
N
1
2
P
1
2
T
1
2
U
1
2
L13 N
1
3
R
1
3
L10 T
1
3
T
1
0
K
1
4
L14 N
1
4
P
1
4
A
C
4
A
C
6
A
C
8
A
C
1
0
E
2
3
D
2
2
AA4 W4 AB4 Y4
T
1
4
K
1
5
N
1
5
T
1
5
M
1
6
N
1
6
R
1
6
R
1
2
K
1
3
P
1
3
U
1
3
M
1
4
R
1
4
H
2
3
J2
3
M
2
3
P
2
3
L23 T
2
3
V
2
3
R
2
3
Y
2
3
AA23 AB23 A
C
2
3
W
2
3
F
2
3
P
1
1
M
1
0
M
1
7
P
1
7
R
1
7
P
1
0
L17
A
C
1
2
A
D
1
2
A
D
1
3
A
D
2
0
A
C
2
2
A
C
2
1
A
C
1
3
A
C
1
4
A
C
1
5
A
C
1
9
A
C
2
0
A
D
1
9
A
D
1
7
AE17
A 2 6
B 2 6
J2
4
W
2
5
K
2
5
K
2
3
K
2
6
W
2
4
A5 A7 B7 C7 D7 A
1
1
A3 A4 D6 C6 C8 C9 C
1
0
D8 D9 D
1
0
C
1
1
C
1
3
D
1
3
E1 E2 C4 E4 D4
A2 B3 D3 E3 F4 F2 G1 H3 H1 J3 J1
F3 G2 H4 H2 J4 J2 K4
A E 8
A F 8
A C9
A D9
A E 9
A F 9
A D1 0
A E 1 0
A F 1 0
A C1 1
A D1 1
A E 1 1
A F 1 1
A F 1 2
A E 1 2
A F 1 3
A E 1 3
A F 1 4
A E 1 4
A D1 4
A F 1 5
A E 1 5
A F 1 6
A E 1 6
B 1 7
B5 D
1
1
D1 2
A
1
3
B
1
3
D
1
7
D
2
3
B4
V CL K
V ODD
V V S
V HS_ CS YNC
V DV
GP IO_ 1 4
GP IO_ 1 5
OE XT R
NO_ CONNE CT
DCL K
F S BK S E L 1
F S BK S E L 0
F S CK E
F S RA S
F S W E
F S CA S
F S DQM 0
OCM DA T A 0
OCM DA T A 1
OCM DA T A 2
OCM DA T A 3
OCM DA T A 4
OCM DA T A 5
OCM DA T A 6
OCM DA T A 7
OCM DA T A 8
OCM DA T A 9
OCM DA T A 1 0
OCM DA T A 1 1
OCM DA T A 1 2
OCM DA T A 1 3
OCM DA T A 1 4
OCM DA T A 1 5
OCM ADDR0
OCM ADDR1
OCM ADDR2
OCM ADDR3
OCM ADDR4
OCM ADDR5
OCM ADDR6
OCM ADDR7
OCM ADDR8
OCM ADDR9
OCM ADDR1 0
OCM ADDR1 1
OCM ADDR1 2
OCM ADDR1 3
OCM ADDR1 4
OCM ADDR1 5
OCM ADDR1 6
OCM ADDR1 7
OCM ADDR1 8
OCM ADDR1 9
/OCM _ CS0
/OCM _ CS1
/OCM _ CS2
/OCM _ INT 1
/OCM _ INT 2
/ROM _ CS
/OCM _ RE
/OCM _ W E
/RE S ET
A HSY NC
A V SY NC
V GA_ S CL
V GA_ S DA
DV I_ SCL
DV I_ SDA
IR1
IR0
OCM _ UDI
OCM _ UDO
M S T R_ S CL
M S T R_ S DA
E X TCL K
F S ADDR0
F S ADDR1
F S ADDR2
F S ADDR3
F S ADDR4
F S ADDR5
F S ADDR6
F S ADDR7
F S ADDR1 0
F S ADDR1 1
F S ADDR9
F S ADDR8
F S DA T A 0
F S DA T A 1
F S DA T A 2
F S DA T A 3
F S DA T A 4
F S DA T A 5
F S DA T A 6
F S DA T A 7
F S DA T A 8
F S DA T A 9
F S DA T A 1 0
F S DA T A 1 1
F S DA T A 1 2
F S DA T A 1 3
F S DA T A 1 4
F S DA T A 1 5
F S DA T A 1 6
F S DA T A 1 7
F S DA T A 1 8
F S DA T A 1 9
F S DA T A 2 0
F S DA T A 2 1
F S DA T A 2 2
F S DA T A 2 3
F S DA T A 2 4
F S DA T A 2 5
F S DA T A 2 6
F S DA T A 2 7
F S DA T A 2 8
F S DA T A 2 9
F S DA T A 3 0
F S DA T A 3 1
F S DQM 3
F S DQM 2
F S DQM 1
F S DQS
F S CL K p
F S CL K n
S V DA T A 0
S V DA T A 1
S V DA T A 2
S V DA T A 3
S V DA T A 4
S V DA T A 5
S V DA T A 6
S V DA T A 7
S V ODD
S V VS Y NC
S V HS Y NC
S V CL K
S V DV
V RED0
V RED1
V RED2
V RED3
V RED4
V RED5
V RED6
V RED7
V GRN0
V GRN1
V GRN2
V GRN3
V GRN4
V GRN5
V GRN6
V GRN7
V B L U0
V B L U1
V B L U2
V B L U3
V B L U4
V B L U5
V B L U6
V B L U7
P W M 0
P W M 1
P W M 2
OCM _ T I M E R1
NO_ CONNE CT
NO_ CONNE CT
RX C-
RX C+
RX 2 -
RX 2 +
RX 1 +
RX 1 -
RX 0 +
RX 0 -
RE XT
L B ADC_ IN1
L B ADC_ IN2
L B ADC_ IN3
NO_ CONNE CT
B L UE -
B L UE +
GREE N-
GREE N+
RE D-
RE D+
S OG
NO_ CONNE CT
T CL K
X T AL
NO_ CONNE CT
A CS_ RS ET _ HD
GP IO_ G0 6 _ B0
GP IO_ G0 6 _ B1
GP IO_ G0 6 _ B2
GP IO_ G0 6 _ B3
A 3 +
A 3 -
A C+
A C-
GP IO_ G0 5 _ B0
A 2 +
A 2 -
GP IO_ G0 5 _ B3
A 1 +
A 1 -
A 0 +
A 0 -
GP IO_ G0 4 _ B0
GP IO_ G0 4 _ B1
GP IO_ G0 4 _ B2
GP IO_ G0 4 _ B3
GP IO_ G0 4 _ B4
GP IO_ G0 4 _ B5
GP IO_ G0 4 _ B6
GP IO_ G0 4 _ B7
D_ GND
GP IO_ G0 8 _ B5 /J T A G_ RE S ET
GP IO_ G0 8 _ B4 /J T A G_ T DO
GP IO_ G0 8 _ B3
GP IO_ G0 8 _ B2 /J T A G_ T DI
GP IO_ G0 8 _ B1 /J T A G_ M ODE
GP IO_ G0 8 _ B0 /J T A G_ CL K
GP IO_ G0 9 _ B5
GP IO_ G0 9 _ B4
GP IO_ 1 6
GP IO_ G0 9 _ B3
GP IO_ G0 9 _ B2
GP IO_ G0 9 _ B1
GP IO_ G0 9 _ B0
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
C
OR
E
_
1
.8
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
IO_
3
.3
IO_
3
.3
IO_
3
.3
IO_
3
.3
F
S
_
2
.5
IO_
3
.3
IO_
3
.3
IO_
3
.3
IO_
3
.3
IO_
3
.3
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
F
S
_
2
.5
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
D
_
G
N
D
L
V
D
S
B
_
3
.3
L
V
D
S
B
_
3
.3
L
V
D
S
B
_
3
.3
L
V
D
S
A
_
3
.3
L
V
D
S
A
_
3
.3
L
V
D
S
A
_
3
.3
L
V
D
S
B
_
G
N
D
L
V
D
S
B
_
G
N
D
L
V
D
S
B
_
G
N
D
V
S
S
A
3
3
A
_
L
V
D
S
V
S
S
A
3
3
A
_
L
V
D
S
V
S
S
A
3
3
A
_
L
V
D
S
V
S
S
D
3
3
_
L
V
D
S
V
D
D
D
3
3
_
L
V
D
S
P P W R
P B IA S
F
S
V
R
E
F
F
S
V
R
E
F
V
S
S
A
1
8
_
D
L
L
V
D
D
A
1
8
_
D
L
L
F
S
V
R
E
F
V
S
S
F
S
V
R
E
F
V
S
S
A
D
C
_
D
GN
D
D
V
I_
G
N
D
D
V
I_
G
N
D
D
V
I_
G
N
D
D
V
I_
G
N
D
D
V
I_
G
N
D
A
D
C
_
1
.8
A
D
C
_
1
.8
D
V
I_
1
.8
D
V
I_
3
.3
D
V
I_
3
.3
D
V
I_
3
.3
D
V
I_
3
.3
D
V
I_
1
.8
D
V
I_
1
.8
D
V
I_
1
.8
D
V
I_
3
.3
L
B
A
C
D
-3
3
L
B
A
D
C
_
G
N
D
A
D
C
_
A
GN
D
A
D
C
_
A
GN
D
A
D
C
_
A
GN
D
A
D
C
_
A
GN
D
A
D
C
_
A
GN
D
A
D
C
_
3
.3
A
D
C
_
3
.3
A
D
C
_
3
.3
A
D
C
_
3
.3
V
D
D
A
3
3
_
R
P
L
L
V
D
D
A
3
3
_
P
L
L
V
D
D
A
3
3
_
F
P
L
L
V
D
D
A
3
3
_
S
D
D
S
V
D
D
A
3
3
_
S
D
D
S
V
D
D
A
3
3
_
D
D
D
S
V
D
D
A
3
3
_
D
D
D
S
V
S
S
A
3
3
_
R
P
L
L
V
S
S
D
3
3
_
P
L
L
V
S
S
A
3
3
_
F
P
L
L
V
S
S
A
3
3
_
S
D
D
S
V
S
S
D
3
3
_
S
D
D
S
V
S
S
A
3
3
_
D
D
D
S
V
S
S
D
3
3
_
D
D
D
S
GP IO_ G0 7 _ B0
GP IO_ G0 7 _ B1
GP IO_ G0 7 _ B2
GP IO_ G0 7 _ B3
GP IO_ G0 7 _ B4
GP IO_ G0 7 _ B5
GP IO_ G0 7 _ B6
GP IO_ G0 7 _ B7
L V DS _ S HI E L D[0 ]
L V DS _ S HI E L D[1 ]
L V DS _ S HI E L D[2 ]
L V DS _ S HI E L D[3 ]
B 3 +
B 3 -
B C+
B C-
L V DS _ S HI E L D[4 ]
B 2 +
B 2 -
L V DS _ S HI E L D[5 ]
B 1 +
B 1 -
B 0 +
B 0 -
V CL A M P
D
V
I_
G
N
D
D
V
I_
G
N
D
L B ADC_ RE T URN
D
_
G
N
D
D
_
G
N
D
IO_
3
.3
IO_
3
.3
A
D
C
_
D
GN
D
P R4 1 2 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
To 4052 Audio IN Selector
F S DA T A 2 7
F S DA T A 1 6
A DC_ IN2
/F S DAT A U6
T X A3 +
/F S DAT A U1 0
C4 8 6
0 .1 u F/ 1 6 V
FSCL K+ 9
F S DA T A 1 0
OCM DA T A 7
R4 3 5
1 0 K£ [ 1 /1 6 W
A DC_ B 1
/RE S ET 3 .3 V
+
C4 8 2
1 0 u F /1 6 V
+3.3V _DV I
A D_COA S T 6
S V DA T A 2
CN4 0 2
CONN
GP ROB E
1
2
3
4
C4 3 4
0 .1 u F/ 1 6 V
V GA_ S DA 7 ,1 0
F S DA T A 1 3
/F S B KS E L U0
A DC_ R5
R4 5 3
4 .7 K £ [ 1 /1 6 W
R4 1 4
1 0 K£ [ 1 /1 6 W
MS TR_S CL 4
Ri n 3 + 1 0
F S ADDR1 0
F S DQM 2
C4 5 6
0 .1 u F/ 1 6 V
S E C_ S DA 2 ,3 ,5 ,6 , 1 0
OCM ADDR4
/F S DQM 2
C4 6 1
0 .1 u F/ 1 6 V
C4 9 7
0 .1 u F/ 1 6 V
+3.3V _DV I
P W R_ ON 1 0 ,1 2
/F S DAT A U3
/OCM _ RE
W P
P R4 0 5 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5 C4 5 4
0 .1 u F/ 1 6 V
+ 3 .3 V_ L V DS
A DC_G[0..7] 6
S E C_ S CL 2 ,3 ,5 ,6 , 1 0
F S DA T A 2 3
R4 0 7 1 0 K£ [ 1 /1 6 W
+
C5 0 3
2 2 u F /1 6 V
R4 1 0
1 0 K£ [ 1 /1 6 W
C4 5 7
0 .1 u F/ 1 6 V
/OCM _ CS
Max trace length on this interfce is 2.5 inches
Inverter Protector
S V CLK 4
OCM ADDR1 8
C4 2 2
0 .1 u F/ 1 6 V
C4 9 6
0 .1 u F/ 1 6 V
+
C4 8 4
2 2 u F /1 6 V
P B IA S
F S DA T A 2 6
F S DA T A 2 9
T X A1 +
F S CA S
+5V P
A UDI O_ S L 1 1 1
S V CL K
A DC_ G3
T 4 1 NC
C5 1 1
0 .1 u F/ 1 6 V
P R4 0 4 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
C4 3 2
0 .1 u F/ 1 6 V
To E_frame
Ri n 1 + 1 0
FSBKSEL1 9
/F S DAT A U2 7
C4 6 0
0 .1 u F/ 1 6 V
R4 5 2
4 .7 K £ [ 1 /1 6 W
F S DA T A 4
/F S DQM 0
/F S A DDRU1
FSCLK+, FSCLK- should be routed like a differentail pair
To E_frame
+3.3V _LB A DC
RX D
Q4 0 5
P M B S3 9 0 4
3
2
1
C4 7 4
0 .1 u F/ 1 6 V
R4 0 9 3 3 £ [ 1 /1 6 W
RE D+ 7
A DC_ B 3
C4 9 1
0 .1 u F/ 1 6 V
/F S DAT A U2 2
D4 0 0
L L 4 1 4 8
U4 0 4 C
7 4 L V C1 4
5 6
14
7
C4 2 1
0 .1 u F/ 1 6 V
C4 8 5
0 .1 u F/ 1 6 V
/F S A DDRU7
F S ADDR9
C4 7 0
0 .1 u F/ 1 6 V R4 0 6 2 4 0 £ [ 1 /1 6 W
U4 0 4 D
7 4 L V C1 4
9 8
14
7
W _ E NA B L E 1 0
T X AC-
/F S A DDRU2
M S T R_ S DA
C4 8 0
0 .1 u F/ 1 6 V
C4 6 7
0 .1 u F/ 1 6 V
P R4 0 6 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
Minimiz e trace length difference between DQS and data and
among the data lines
G
08. G M160 1
AOC (Top Victory) Electronics Co., Ltd.
D
8
1 2
T h u r s d a y , Oc to b e r 2 0 , 2 0 0 5
T i t l e
S i z e Do c u m e n t Nu m b e r Re v
Da te : S h e e t o f
Remote 10
V1 _Vs 6
/FSCAS 9
SOGOUT 6
A DC_ G2
OCM ADDR1 1
/F S DAT A U2 0
/F S DAT A U1 2
F S ADDR0
S V DA T A 0
C4 5 9
0 .1 u F/ 1 6 V
C4 7 3
0 .1 u F/ 1 6 V
+3.3V _A DC
+3.3V _LV DS A
+ 3 .3 V_ L V DSA
A UDI O_ S L 4 1 1
F S DA T A 1 9
/F S DAT A U1 5
L 4 0 5
0 £ [ 1 /8 W
For 3230D I2C
F S DA T A 3 1
C4 5 8
0 .1 u F/ 1 6 V
+
C4 9 4
2 2 u F /1 6 V
C4 3 7
0 .1 u F/ 1 6 V
P R4 1 4 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
TO LVDS Panal
HS _OUT 6
OCM ADDR3
/RE S ET 3 .3 V
C4 2 5
0 .1 u F/ 1 6 V
C4 4 0
0 .1 u F/ 1 6 V
+ 1 .8 V_ DV I
/F S W E
F S CK E
F S DQM 0
C4 6 2
0 .1 u F/ 1 6 V
Ri n 2 + 1 0
OCM DA T A 3
/F S DAT A U2 8
OCM ADDR1 9
/F S DAT A U1 3
P R4 1 6 3 3 £ [ 1 /1 6 W
1
2
3
4 8
7
6
5
From AD 9883
3 V RS T 3
A DC_ R7
W P
C4 4 1
0 .1 u F/ 1 6 V
+3.3V _DIG
V IDE O_ S L 1 2
F S DA T A 2 2
M S T R_ S CL
TO Flash ROM 29LV040B
+5V P
F S DA T A 2 0
U400
24LC32-S N
S OP- 8
1
2
3
4
5
6
7
8
A 0
A 1
A 2
V S S S I
S CK
W P
V CC
C4 9 5
0 .1 u F/ 1 6 V
TO FRAME MEMORY MT46V2M32LG-4
FSCL K- 9
OCM DA T A 0
F S CL K -
R4 0 0
1 0 K£ [ 1 /1 6 W
To 4052 Audio IN Selector
+3.3V _DIG
OCM DA T A 1
F S ADDR5
R4 2 4
1 K £ [ 1 /1 6 W
A CK 1 0
F S BK S E L 0
C4 9 8
0 .1 u F/ 1 6 V
+3.3V _DIG
S T B 1 0
A DC_ B 2
M S T R_ S CL
P P W R
R4 3 8
3 .3 K £ [ 1 /1 6 W
AD_Cla m p 6
F S DA T A 2
OCM DA T A 6
T X A3 -
C4 9 9
0 .1 u F/ 1 6 V
R4 1 3
1 K £ [ 1 /1 6 W
From AD 9883 & E_frame
A DC_ R3
/F S DAT A U1 8
U4 0 5
T CM 8 1 0 L
1
2
3
GND
R
S
T
V
C
C
C5 0 7
0 .1 u F/ 1 6 V
C4 5 1
0 .1 u F/ 1 6 V
C4 5 5
0 .1 u F/ 1 6 V
P W M 0
OCM ADDR0
X T AL
R4 5 0 0 £ [ 1 /1 6 W
To E_frame
A DC_ R2
R4 3 7
1 0 K£ [ 1 /1 6 W
C4 4 3
0 .1 u F/ 1 6 V
+2.5V _DDR
/F S DAT A U2 6
C4 5 3
NC
R4 3 9
2 .7 K £ [ 1 /1 6 W
X 4 0 0
1 4 .3 1 8 M Hz
D4 0 1
L E D
+5V P
FSDQS 9
F S DA T A 1 8
A DC_ B 5
A DC_ G5
F S CL K U+
C4 6 8
0 .1 u F/ 1 6 V
P R4 1 3 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
+5V P
/F S A DDRU0
/F S DAT A U9
OCM ADDR1 5
CN4 0 3
CON8 A
1 2
3 4
5 6
7 8
V D_ RS T 4 ,1 0
F S DA T A 0
F S DA T A 7
OCM DA T A 5
+
C4 8 9
2 2 u F /1 6 V
R4 4 2 1 0 K£ [ 1 /1 6 W
P R4 0 7 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
+5V P
/F S DAT A U3 0
C4 8 1
0 .1 u F/ 1 6 V
T 4 6 NC
P R4 1 1 3 3 £ [ 1 /1 6 W 1
2
3
4 8
7
6
5
Place Series termination resistors on bidirectional lines-DATA and DQS
midway between gm1601 BGA and memory
RCL K + 1 0
F S DA T A 6
OCM ADDR8
M S T R_ S CL
To 4052 Video IN Selector
MS TR_S DA 4
Ri n 1 - 1 0
F S W E
R4 1 5
2 2 0 £ [ 1 /1 6 W
+3.3V _LV DS
K E Y_ I_ 1 1 0
OCM ADDR1 7
T X AC+
A DC_ G0
From AD9883 HSOUT & VSOUT
F S ADDR1
+3.3V _DIG
S RS_ ON/OF F 5
S V DA T A 4
C4 7 6
3 3 p F
C4 9 2
0 .1 u F/ 1 6 V
K E Y_ I_ 3 1 0
B L UE - 7
A DC_ R4
/OCM _ CS0
Q4 0 7
P M B S3 9 0 4
3
2
1
C4 4 9
0 .1 u F/ 1 6 V
C4 5 0
0 .1 u F/ 1 6 V
+3.3V _P LL
+ 3 .3 V_ DV I
V IDE O_ S L 2 2
V GA_ CA B 7
OCM ADDR1 6
C5 0 1
0 .1 u F/ 1 6 V
C4 4 7
0 .1 u F/ 1 6 V
C4 2 7
0 .1 u F/ 1 6 V
A DC_B [0..7] 6
F S ADDR4
S V DA T A 5
R4 4 1 1 0 K£ [ 1 /1 6 W
C4 9 0
0 .1 u F/ 1 6 V
/OCM _ W E 9
V GA_ S CL 7 ,1 0
R4 2 1
6 2 0 £ [ 1 /1 6 W
R4 2 7
4 .7 K £ [ 1 /1 6 W
K E Y_ I_ 2 1 0
A DC_ B 6
C4 8 8
0 .1 u F/ 1 6 V
C4 7 7
0 .1 u F
R4 4 0
2 .7 K £ [ 1 /1 6 W
From AD 9883
B A CK _ L IGHT_ A DJ1 0
V1 _Hs 6
/OCM _ CS 9
A DC_ B 7
OCM ADDR1 0
/F S A DDRU4
R4 1 2
2 2 0 £ [ 1 /1 6 W
C4 3 3
0 .1 u F/ 1 6 V
To 4052 Video IN Selector
B K L T _ ON
A DC_ B 0
C4 3 1
0 .1 u F/ 1 6 V
Q4 0 2
P M B S3 9 0 4
3
2
1
R4 3 6
1 0 K£ [ 1 /1 6 W
IR1
F S ADDR7
T X A2 -
P W M 0
S V DV
R4 2 2
1 0 K£ [ 1 /1 6 W
C4 2 6
0 .1 u F/ 1 6 V
FSBKSEL0 9
A DC_ B 4
+1.8V _DV I
F S DA T A 3
A DC_ R0
/F S DAT A U2 5
C4 7 1
0 .1 u F/ 1 6 V
+
C4 1 9
2 2 u F /1 6 V
C5 0 0
0 .1 u F/ 1 6 V
Q4 0 0
A O4 4 0 3
1 2 3 4
8 7 6 5
S1 S1 S1 G1
D1 D1 D1 D1
R4 5 5
0 £ [ 1 /1 6 W
C4 7 9
0 .1 u F/ 1 6 V
P P W R
Panal 5V B+ Enable
+3.3V _LV DS B
F S DA T A 3 0
A DC_ G4
/OCM _ CS2
/F S CAS
R4 1 8 1 K £ [ 1 /1 6 W
DVI Input No use