ezTrainer
User Manual
FPGA MADE eAzY
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Anaya Tech Systems Pvt Ltd
the standard Reduced Media Independent Interface (RMII). See table below for connectivity:
Please note that the PHY should be out of reset through FPGA pin number 199, before any communication can
proceed.The Ethernet cable needs to be connected to the connector RJ300.
5.7 LCD INTERFACE
A standard 2-row (16 character each) LCD is connected to the FPGA as shown below. The LCD has to be used
in a 4-bit data format (only signals needed are RS, ENABLE, DB4-DB7. DB0-DB3 are not used.
5.8 VGA INTERFACE
A VGA monitor can be used to implement display projects using the FPGA. The interface from the FPGA to the
15-pin VGA connector is as shown below:
Table 6:
Signal Names
FPGA Pin
Transceiver pin
MDC
205
19
MDIO
206
18
TXEN
203
34
TXD0
202
35
TXD1
200
36
RXDV
204
27
RXD0
194
23
RXD1
184
22
RESET
199
47
CLOCK (50 MHz)
183
15
Table 7:
Signal Names
FPGA Pin
LCD pin
RS
205
4
ENABLE
206
6
DB4
203
11
DB5
202
12
DB6
200
13
DB7
204
14
Table 8:
Signal Names
FPGA Pin
VGA connector pin
RED
167
1
GREEN
168
2
BLUE
171
3
