A2541R24x
– User’s Manual
Page 9 of 36
Release Date 11/22/13
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Power management ensures a stable supply for the internal functions, as well as
providing means for a low power sleep mode.
CPU and Memory
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The 8051 CPU core used in the CC2541 device is a single-cycle 8051-
compatible core. It has three different memory-access buses (SFR, DAT and
CODE/XDATA) with single-cycle access to SFR, DATA, and the main SRAM. It
also includes a debug interface and an 18-input extended interrupt unit.
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The memory arbiter connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus.
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The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA
memory spaces. This is an ultralow-power SRAM that retains its contents even
when the digital part is powered off.
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256 KB flash block provides in-circuit programmable non-volatile program
memory for the device, and maps into the CODE and XDATA memory spaces. In
addition to holding the program code, it also allows the application to save data
that must be preserved such that it is available after restarting the device.
I/O Controller
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The I/O controller is responsible for all general-purpose I/O pins. The CPU can
configure whether peripheral modules control certain pins or they are under
software control, and if so, whether they are configured as input or output.
Step-Down Converter (TPS62730)
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The step-down converter (TPS62730, DC-DC Converter) provides a fixed 2.1V
input voltage to the transceiver chip internally when it is in DC-DC mode and the
module input voltage is above 2.3V.
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BYPASS mode with a typical 30nA current consumption supports the module’s
sleep and low power modes.
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The step-down converter can be controlled via firmware or by an external signal
on module pin 16. When controlled by firmware the converter is placed into
Bypass mode whenever the CC2541 is in a low-power state, otherwise the
converter is ON (i.e. switching). This helps reduce overall power consumption for
systems operating above 2.1V since the CC2541 device is powered by the
output of the TPS62730 instead of the radio module’s supply pin. That equates to
about 30% reduction in current draw while the radio is in a higher power active
state when operating at 3.0V and about 40% reduction in current when operating
at 3.6V (current reduction is at module input).
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When the converter is in DC-
DC mode the radio module’s I/O signals will be at
2.1V logic levels, whereas in Bypass mode the I/O will be at logic levels equal to
the module’s supply voltage. This is an important consideration when deciding
whether to force the DC-DC converter into Bypass mode or allow firmware to
cycle between ON and Bypass. In the latter scenario, all devices that interface to
the A2541 must be compatible with the changing logic levels.
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Connections to the step-down converter pins are identified in Figure 3 below. For
brevity, filtering components are not shown.
