UG-157
Evaluation Board User Guide
Rev. 0 | Page 8 of 12
EVALUATION BOARD SCHEMATICS AND ARTWORK
0913
7-
009
BUCK1
BUCK2
LDO1
LDO2
SW1
SW2
VOUT1
VOUT2
VOUT1
VOUT2
PGND1
PGND2
VOUT3
VOUT4
L1
CBMF1606
L2
CBMF1606
VIN1
D2
C2
D1
D3
C3
D4
A1
A4
VIN2
VIN3
VIN4
AGND
MODE
LEDI
LEDO
ADP5032
U1
C1
C4
A2
A3
B1
B2
B3
B4
JP11
VOUT1
JP12
VOUT2
JP13
VIN
1
2
1
2
1
2
D4
INDICATOR LED
C6
4.7µF
CD402STD
C7
1µF
CD402STD
C5
4.7µF
CD402STD
J2
VIN_1
VIN_2
VIN1
VIN2
VIN4
VIN3
J1
J8
PGND
J6
VOUT2
J9
PGND
J7
VOUT3
J10
PGND
VOUT1
J5
C4
1µF
CD402STD
J11
GND1
J12
GND2
3
JP3
MODE
2
1
3
2
1
3
JP4
LEDIN
2
1
3
2
1
COUT_1
10µF
CD603STD
COUT_2
10µF
CD603STD
COUT_3
1µF
CD402STD
J14
VOUT4
J13
PGND
COUT_4
1µF
CD402STD
Figure 9. Evaluation Board Schematic of ADP5032
0
91
37-01
0
Figure 10. Top Layer, Recommended Layout