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Analog Devices SHARC ADSP-21020, Specification Sheet

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Analog Devices SHARC ADSP-21020 Specification Sheet Download Page 11

ADSP-21020

REV. C

–11–

Table Vll. Multifunction Compute Operations

Fixed-Point

Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12
Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12
Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2
MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12
MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12
MRF=MRF + R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2
Rm=MRF + R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12
Rm=MRF + R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12
Rm=MRF + R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2
MRF=MRF – R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12
MRF=MRF – R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12
MRF=MRF – R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2
Rm=MRF – R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12
Rm=MRF – R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12
Rm=MRF – R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2
Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12,

Rs=R11-8 – R15-12

Floating-Point

Fm=F3-0 * F7-4, Fa=F11-8 + F15-12
Fm=F3-0 * F7-4, Fa=F11-8 – F15-12
Fm=F3-0 * F7-4, Fa=FLOAT R11-8 by R15-12
Fm=F3-0 * F7-4, Fa=FIX R11-8 by R15-12
Fm=F3-0 * F7-4, Fa=(F11-8 + F15-12)/2
Fm=F3-0 * F7-4, Fa=ABS F11-8
Fm=F3-0 * F7-4, Fa=MAX (F11-8, F15-12)
Fm=F3-0 * F7-4, Fa=MIN (F11-8, F15-12)
Fm=F3-0 * F7-4, Fa=F11-8 + F15-12,

Fs=F11-8 – F15-12

Ra, Rm

Any register file location (fixed-point)

R3-0

R3, R2, R1, R0

R7-4

R7, R6, R5, R4

R11-8

R11, R10, R9, R8

R15-12

R15, R14, R13, R12

Fa, Fm

Any register file location (floating-point)

F3-0

F3, F2, F1, F0

F7-4

F7, F6, F5, F4

F11-8

F11, F10, F9, F8

F15-12

F15, F14, F13, F12

(SSF)

X-input signed, Y-input signed, fractional inputs

(SSFR)

X-input signed, Y-input signed, fractional inputs, rounded output

Table VIII. Interrupt Vector Addresses and Priorities

Vector
Address

No.

(Hex)

Function

0

0x00

Reserved

1*

0x08

Reset

2

0xl0

Reserved

3

0xl8

Status stack or loop stack overflow or

PC stack full

4

0x20

Timer=0 (high priority option)

5

0x28

IRQ3

 asserted

6

0x30

IRQ2

 asserted

7

0x38

IRQ1

 asserted

8

0x40

IRQ0

 asserted

9

0x48

Reserved

10

0x50

Reserved

11

0x58

DAG 1 circular buffer 7 overflow

12

0x60

DAG 2 circular buffer 15 overflow

13

0x68

Reserved

14

0x70

Timer=0 (low priority option)

15

0x78

Fixed-point overflow

16

0x80

Floating-point overflow

17

0x88

Floating-point underflow

18

0x90

Floating-point invalid operation

19–23

0x98-0xB8

Reserved

24–31

0xC0–OxF8

User software interrupts

*Nonmaskable

Summary of Contents for SHARC ADSP-21020

Page 1: ...IEEE Floating Point Data Formats 32 Bit Fixed Point Formats Integer and Fractional with 80 Bit Accumulators IEEE Exception Handling with Interrupt on Exception Three Independent Computation Units Mul...

Page 2: ...runtime library with over 100 standard and DSP specific functions C Source Level Debugger A full featured C source level debugger that works with the simulator or EZ ICE emulator to allow debugging o...

Page 3: ...e of the ADSP 21020 allow the following nine data transfers to be performed every cycle Off chip read write of two operands to or from the register file Two operands supplied to the ALU Two operands s...

Page 4: ...egister every cycle When this count register reaches zero the ADSP 21020 generates an interrupt and asserts its TIMEXP output The count register is automatically reloaded from a 32 bit period register...

Page 5: ...ory address lines and provide an early indication of a possible bus cycle PMRD O Program Memory Read strobe This pin is asserted when the ADSP 21020 reads from program memory PMWR O Program Memory Wri...

Page 6: ...ins IGND G Power supply return for internal circuitry 7 pins TCK I Test Clock Provides an asynchronous clock for JTAG boundary scan TMS I S Test Mode Select Used to control the test state machine TMS...

Page 7: ...d IF condition compute dreg DM data6 Ia PM data6 Ic 5 IF condition compute ureg1 ureg2 6a IF condition shiftimm DM Ia Mb dreg PM Ic Md 6b IF condition shiftimm dreg DM Ia Mb PM Ic Md 7 IF condition co...

Page 8: ...PM addr24 15a DM data32 Ia ureg PM data24 Ic 15b ureg DM data32 Ia PM data24 Ic 16 DM Ia Mb data32 PM Ic Md 17 ureg data32 MISCELLANEOUS INSTRUCTIONS 18 BIT SET sreg data32 CLR TGL TST XOR 19a MODIFY...

Page 9: ...of last program memory address System Registers MODE1 Mode control bits for bit reverse alternate reg isters interrupt nesting and enable ALU satu ration floating point rounding mode and boundary MODE...

Page 10: ...t format for 1 input operations SSF Default format for 2 input operations Table VI Shifter and Shifter Immediate Compute Operations Shifter Shifter Immediate Rn LSHIFT Rx BY Ry Rn LSHIFT Rx BY data8 R...

Page 11: ...F3 0 F7 4 Fa MIN F11 8 F15 12 Fm F3 0 F7 4 Fa F11 8 F15 12 Fs F11 8 F15 12 Ra Rm Any register file location fixed point R3 0 R3 R2 R1 R0 R7 4 R7 R6 R5 R4 R11 8 R11 R10 R9 R8 R15 12 R15 R14 R13 R12 Fa...

Page 12: ...A and IDDIN typical 115 mA See Power Dissipation for calculation of external EVDD supply current for total supply current 8 Applies to IVDD pins Idle refers to ADSP 21020 state of operation during exe...

Page 13: ...Low 10 10 10 10 ns CLKIN tCKH tCKL tCK Figure 3 Clock Reset K B T Grade K B T Grade B T Grade K Grade 20 MHz 25 MHz 30 MHz 33 3 MHz Frequency Dependency Parameter Min Max Min Max Min Max Min Max Min M...

Page 14: ...ll be latched in that cycle Meeting the pulse width is not necessary if the setup and hold is met Likewise meeting the setup and hold is not necessary if the pulse width is met See the Hardware Config...

Page 15: ...rted Switching Characteristic tDFO FLAG3 0OUT Delay from CLKIN High 24 24 24 24 ns tHFO FLAG3 0OUT Hold after CLKIN High 5 5 5 5 ns tDFOE CLKIN High to FLAG3 0OUT Enable 1 1 1 1 ns tDFOD CLKIN High to...

Page 16: ...isable to BG Low 2 2 2 2 ns tDME CLKIN High to Memory Interface Enable 25 20 16 15 25 DT 2 ns tDBGL CLKIN High to BG Low 22 22 22 22 ns tDBGH CLKIN High to BG High 22 22 22 22 ns NOTES DT tCK 50 ns Me...

Page 17: ...S xTS Delay after XRD XWR Low 16 11 7 6 16 DT 2 ns Switching Characteristic tDTSD Memory Interface Disable before CLKIN High 0 2 4 5 DT 4 ns tDTSAE xTS High to Address Select Enable 0 0 0 0 ns NOTES D...

Page 18: ...tDAAK xACK Delay from Address 27 18 12 9 27 7DT 8 ns tDRAK xACK Delay from xRD Low 15 10 6 5 15 DT 2 ns tSAK xACK Setup before CLKIN High 14 12 10 9 14 DT 4 ns tHAK xACK Hold after CLKIN High 0 0 0 0...

Page 19: ...ADSP 21020 REV C 19 CLKIN DATA DMACK PMACK ADDRESS SELECT DMPAGE PMPAGE tDARL tDAP tDAAK tDCKRL tDRAK tSAK tHAK tDAD tDRLD tRWR tHDRH tRW tHDA DMWR PMWR DMRD PMRD Figure 10 Memory Read...

Page 20: ...7 5 3 11 3DT 8 ns tWW xWR Pulse Width 26 20 16 15 26 9DT 16 ns tDDWH Data Setup before xWR High 23 18 14 13 23 DT 2 ns tDWHA Address Select Hold after xWR Deasserted 1 0 0 0 1 DT 16 ns tHDWH Data Hold...

Page 21: ...ADSP 21020 REV C 21 CLKIN DATA DMACK PMACK ADDRESS SELECT DMPAGE PMPAGE tDAWL tDAP tDAAK tDCKWL tDWAK tSAK tHAK tWDE tDWHA tWWR tDDWR tDDWH tWW tDAWH tHDWH DMWR PMWR DMRD PMRD Figure 11 Memory Write...

Page 22: ...s Setup before TCK High 7 7 7 7 ns tHSYS System Inputs Hold after TCK High 9 9 9 9 ns tTRSTW TRST Pulse Width 200 160 132 120 ns Switching Characteristic tDTDO TDO Delay from TCK Low 15 15 15 15 ns tD...

Page 23: ...ADSP 21020 REV C 23 TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS tSTAP tHTAP tDTDO tSSYS tHSYS tDSYS tTCK Figure 12 IEEE 1149 1 Test Access Port...

Page 24: ...multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving Example System Hold Time Calculation To determine the data output hold time in a particul...

Page 25: ...Figure 16 Typical Output Rise Time vs Load Capacitance at Maximum Case Temperature 0 200 3 1 50 2 25 4 175 125 100 75 150 LOAD CAPACITANCE pF RISE TIME ns 0 8V 2 0V 1 2 3 59 3 00 1 33 0 85 NOTES 1 OUT...

Page 26: ...can switch on each cycle If only one bank is accessed no select line will switch Example Estimate PEXT with the following assumptions A system with one RAM bank each of PM 48 bits and DM 32 bits 32K 3...

Page 27: ...header such as that shown in Figure 20 The EZ ICE probe plugs directly onto this connector for chip on board emulation you must add this connector to your target board design if you intend to use the...

Page 28: ...I DMWR EVDD DMS3 DMS1 EGND IGND PMD45 PMD43 EGND IGND CLKIN DMRD EGND IGND DMD37 DMD38 EVDD IVDD DMA25 DMA15 DMA10 DMA5 FLAG1 PMA2 PMA7 PMA12 PMA16 PMA22 PMS1 DMA20 IRQ3 EGND EGND IGND IGND IVDD NC PM...

Page 29: ...ST PMS1 PMA23 PMA19 DMS3 DMPAGE DMA30 DMA26 DMA25 DMS2 DMA29 PMD21 PMD26 PMD23 PMD18 PMD19 PMD16 PMD12 PMD13 PMA14 PMA11 PMA10 PMA9 PMA5 PMA4 PMA1 18 17 16 15 14 U T S R P 18 17 16 15 14 U T S R P DMA...

Page 30: ...A23 T12 DMACK T3 PMD32 U15 EGND C14 DMA24 L17 PMA0 R5 PMD33 D11 IGND B15 DMA25 M18 PMA1 S4 PMD34 G4 IGND B14 DMA26 M15 PMA2 U2 PMD35 G15 IGND D12 DMA27 M16 PMA3 S5 PMD36 L4 IGND C13 DMA28 M17 PMA4 T4...

Page 31: ...18 TOP VIEW e1 e1 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0 084 0 102 2 11 2 59 A1 0 40 0 60 1 02 1 52 b 0 018 TYP 0 46 TYP b1 0 050 TYP 1 27 TYP D 1 844 1 876 46 84 47 64 e1 1 700 TYP 43 18 TYP e...

Page 32: ...Grid Array ADSP 21020BG 100 40 C to 85 C 25 40 223 Lead Ceramic Pin Grid Array ADSP 21020BG 120 40 C to 85 C 30 33 3 223 Lead Ceramic Pin Grid Array ADSP 21020TG 80 55 C to 125 C 20 50 223 Lead Cerami...

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