2
Rev. 0
QUICK START PROCEDURE
The DC2611A is easy to set up to evaluate the perfor-
mance of the LTC6955. Follow the procedure below
DC2611A Configuration
1. Connect J27 and J28 to a power supply and apply power
(see Figure 1 and the Typical DC2611A Requirements
and Characteristics table).
2. Connect a low phase-noise (or jitter) single-ended sig-
nal to IN– (J25). Refer to the LTC6955 data sheet for
acceptable input frequencies and amplitudes.
3. Connect desired output (OUT10, OUT8, OUT6, OUT4,
OUT1 or OUT0) to a test instrument or other demo
board to evaluate performance. Terminate the unused
outputs with 50Ω.
4. Ensure SW0:3 are configured to enable the desired
output. Setting SEL[3:1]=H and SEL0=L enables all
outputs. Refer to Table 1 for a list of SEL[3:0] settings
vs output states.
Be sure to power down or terminate any unused RF output
with 50Ω, or poor spurious performance may result.
Troubleshooting
If the LTC6955 does not output a signal
1. Ensure LTC6955 input signal is connected to the
LTC6955 IN– pin, not the LTC6955 IN+ pin.
If DC2611A performance is less than the LTC6955 data
sheet specifications:
1. For unexpected spurious response, verify power sup-
plies are low noise and spurious free power supplies.
Power supplies that are based off a switching regulator
architecture are known to generate spurs on low jitter
clock outputs.
2. For poor phase noise results, verify the phase noise
specifications of the input signal and the phase noise
measurement instrument. Traditional signal sources
and spectrum analyzers have higher phase noise than
the LTC6955 and will degrade measurement results. To
measure phase noise performance it is recommended
to use a low jitter oscillator and a signal source analyzer,
such as Keysight’s (previously Agilent/HP) E5052.
3. Contact the factory for further troubleshooting.
Table 1. LTC6955 SEL[3:0] Settings vs Output States
SEL[3:0]
TEMP
DIODE
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
0x0
Pwrdn
0x1
ON
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
Pwrdn
Pwrdn
Pwrdn
Pwrdn
Pwrdn
0x2
ON
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
Pwrdn
Pwrdn
Pwrdn
0x3
ON
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
Pwrdn
0x4
ON
ON
ON
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
Pwrdn
0x5
ON
ON
Inverted
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
Pwrdn
0x6
ON
ON
ON
ON
ON
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
Pwrdn
0x7
ON
ON
Inverted
ON
Inverted
ON
Pwrdn
ON
Pwrdn
ON
Pwrdn
Pwrdn
0x8
ON
ON
ON
ON
ON
ON
ON
ON
Pwrdn
ON
Pwrdn
Pwrdn
0x9
ON
ON
Inverted
ON
Inverted
ON
Inverted
ON
Pwrdn
ON
Pwrdn
Pwrdn
0xA
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Pwrdn
Pwrdn
0xB
ON
ON
Inverted
ON
Inverted
ON
Inverted
ON
Inverted
ON
Inverted
Pwrdn
0xC
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Pwrdn
0xD
ON
ON
Inverted
ON
Inverted
ON
Inverted
ON
Inverted
ON
Inverted
ON
0xE
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
0xF
ON
Pwrdn
