Analog Devices EZ-KIT Lite ADSP-BF533, Manual, Page: 63 / 108

ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-3
EZ-KIT Lite Hardware Reference
The core voltage and the core clock rate can be set on the fly by the pro-
cessor. The input clock is 27 MHz. A 32.768 kHz crystal supplies the Real
Time Clock (RTC) inputs of the processor. The default mode for the pro-
cessor is Flash boot. See
“Boot Mode Select Jumpers (JP2–1)” on
page 3-10 for information about changing the default boot mode.
External Bus Interface Unit
The External Bus Interface Unit (EBIU) connects an external memory to
the ADSP-BF533 device. It includes a 16-bit wide data bus, an address
bus, and a control bus. Both 16-bit and 8-bit access are supported. On the
EZ-KIT Lite, the EBI unit connects to SDRAM and Flash memory.
32 Mbytes (16M x 16 bits) of SDRAM connect to the synchronous mem-
ory select
0
pin (
~SMS0
). Refer to “Using SDRAM Interface” on page 2-4
for information about configuring the SDRAM. Note that SDRAM clock
is the processor’s Clock Out (
CLK OUT
), which frequency should not
exceed 133 MHz.
Two Flash memory devices are connected to the asynchronous memory
select signals,
~AMS2
through
~AMS0
. The devices provide total of 2 Mbytes
of primary Flash memory, 128 Kbytes of secondary Flash memory, and
64 Kbytes of SRAM. The processor can use this memory for both booting
and storing information during normal operation. Refer to
“Using Flash
Memory” on page 2-5 for details.
All of the address, data, and control signals are available externally via the
extender connectors
P3–1
. The pinout of these connectors can be found in
Appendix B, “Schematics” on page B-1 .