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Evaluation Board User Guide 

UG-487 

 

Rev. 0 | Page 5 of 8 

EVALUATION BOARD SCHEMATICS AND ARTWORK 

 

Figure 3. 

ADuM5010

/

ADuM6010 

Schematic 

 
 
 

N

P

C10A

N

P

C8A

5 4 3 2

1

J4A

R18A

R15A

R16A

3

2

1

R1A

20kΩ

C14A

C12A

R13A

13

17

3

12

4

18

9

20

1

8

14

7

10

6

5

2

19

16

15

11

DUT1A

R14A

C15A

C13A

C11A

C5A

C3A

C6A

C7A

C4A

3

2

1

P3A

5

4

3

2

1

J1A

VISOA

ADuM5010ARSZ

0.1µF

DNI

DNI

JOHNSON142-0701-851

DNI

16.5kΩ

0.1µF

TBD0805

10kΩ

10µF

0.1µF

0.1µF

10µF

MOLEX22-03-2031

JOHNSON142-0701-851

VDDPA

VISOA

VDDPA

VISOA

VISOA

VDDPA

VISOA

VISOA

VDDPA

VDDPA

CW

VDD2

GNDISO

NC

NC

GNDISO

GNDISO

NC

VSEL

VISO

GNDISO

GNDP

VDDP

PDIS

NC

GNDP

GNDP

NC

NC

GNDP

VDD1

2

1

P6A

MTSW-202-12-G-S-730

VDDPA

2

1

P7A

MTSW-202-12-G-S-730

VISOA

1

1083-

002

Summary of Contents for EVAL-ADuM5010EBZ

Page 1: ...rovides a JEDEC standard SSOP20 pad layout as well as support for setting the desired output voltage setting enable control and providing multiple positions for on board loads and bypass capacitors isoPower devices employ high frequency high power switching circuits to enable power transfer across chip scale air core transformers The evaluation board includes EMI mitigation recommendations from th...

Page 2: ... 1 Evaluation Board 1 Revision History 2 PCB Evaluation Goals 3 Connectors 3 Part Configuration Structures 3 Bypass on the PCB 3 Provision for Loading 3 EMI Mitigation 4 High Voltage Capability 4 Evaluation Board Schematics and Artwork 5 Ordering Information 7 Bill of Materials 7 REVISION HISTORY 11 12 Revision 0 Initial Version ...

Page 3: ...s a jumper to be placed between Pin 1 and Pin 2 to disable the converter or between Pin 2and Pin 3 to enable the converter The header can be removed if an external logic source controls the disable function and the signal can be fed directly into Position 2 of the header Control of the VISO voltage is accomplished through a voltage divider that s center node is attached to the VSEL pin as shown in...

Page 4: ...om the PCB stack up This addresses emissions due to large high frequency vertical current flow through vias and traces near the edges Figure 4 shows the top layer guard ring and the bottom layer ground fill as well as the regularly spaced vias in the guard ring that creates a cage type structure to reflect inter plane emissions back into the PCB Figure 5 shows the top layer power fill along with i...

Page 5: ...15 11 DUT1A R14A C15A C13A C11A C5A C3A C6A C7A C4A 3 2 1 P3A 5 4 3 2 1 J1A VISOA ADuM5010ARSZ 0 1µF DNI DNI JOHNSON142 0701 851 DNI 16 5kΩ 0 1µF TBD0805 10kΩ 10µF 0 1µF 0 1µF 10µF MOLEX22 03 2031 JOHNSON142 0701 851 VDDPA VISOA VDDPA VISOA VISOA VDDPA VISOA VISOA VDDPA VDDPA CW VDD2 GNDISO NC NC GNDISO GNDISO NC VSEL VISO GNDISO GNDP VDDP PDIS NC GNDP GNDP NC NC GNDP VDD1 2 1 P6A MTSW 202 12 G S ...

Page 6: ...UG 487 Evaluation Board User Guide Rev 0 Page 6 of 8 Figure 4 Edge Guard on Primary Side Top and Bottom Layers Figure 5 Power Fill Top Layer Primary Side 11083 004 11083 005 ...

Page 7: ...LS Table 1 Quantity Reference Designator Description 1 DUT1A ADuM5010 4 C5A C6A C16A C17A 0 1 µF 25 V 10 0805 2 C4A C15A 10 µF 6 3 V 10 0805 1 R14A 10 kΩ 1 10 W 1 0805 1 R16A 16 5 kΩ 1 10 W 1 0805 1 R1A 20 kΩ resistor VAR 3 8 inch SQ top ADJ 2 J1A J4A SMA edge connector Johnson 142 0701 851 ...

Page 8: ...party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board...

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