EVAL-ADE7903EBZ User Guide
UG-797
Phase Voltage Sense Inputs (V1P_ IN Test Pin)
The phase-to-neutral voltage input connections on the
EVAL-
ADE7903EBZ
evaluation board can be directly connected to the
line voltage source between the GND and V1P_IN test points for
phase-to-neutral voltage. These voltages are attenuated using a
simple resistor divider network before they are supplied to the
ADE7903
. The attenuation network on the voltage channels is
designed so that the corner frequency (3 dB frequency) of the
network matches that of the antialiasing filters in the current
channel inputs. This design prevents the occurrence of large
energy errors at low power factors.
The V1P_IN path in Figure 6 shows a typical connection of the
voltage inputs; the resistor divider consists of three 330 kΩ
resistors (R1, R5, and R10) and one 1 kΩ resistor (R14). The
antialiasing filter R14/C11 matches the R12/C9 filter in the VM
path. The absolute maximum voltages on the V1P and VM pins
of the
ADE7903
are ±2 V. The D1, D7, D4, and D9 diodes
protect the V1P and VM pins against voltages greater than ±2 V.
The maximum signal level permissible at the V1P pin of the
ADE7903
is ±0.5 V peak. The signal range must not exceed
±0.5 V with respect to GND for specified operation.
The E4 and E5 ferrite beads filter the high frequency noise that
may be induced into the wires.
Auxiliary Voltage Sense Inputs (V2P_IN Test Pin)
The auxiliary voltage input connections on the
EVAL-
ADE7903EBZ
evaluation board can be directly connected to
the line voltage sources between V2P_IN and GND for the
auxiliary voltage.
The V2P_IN path in Figure 6 shows a typical connection of the
Phase A auxiliary voltage input. It is very similar to the V1P_IN
path explained in Phase Voltage Sense Inputs (V1P_ IN Test Pin)
section.
Figure 6. Phase Voltage Input Structure on the Evaluation Board
VDD and Ground Pin Management
The
ADE7903
package has four ground pins (GND): Pin 2,
Pin 10, Pin 11, and Pin 20. Figure 7 presents their management,
on the side of the current and voltage inputs, in the case of an
ADE7903
. It is important to note that Pin 11 (GND) must be
connected to either Pin 2 or Pin 10 (GND) outside the package.
Similarly, Pin 19 (VDD) must be connected directly to Pin 1
(VDD) in the shortest path outside of the package because they
are not internally connected. The C1A, C2A, and C4A
decoupling capacitors on the VDD pins are connected to the
closest ground pin. The decoupling capacitors, C5A and C6A
on the analog LDO pin and C13A and C14A on the voltage
reference pin, must be separate from the VDD circuitry and are
connected to ground (Pin 10).
Figure 7. Isolated Ground Pins Management
The P1 meter input constitutes the AGND_ADC1 signal (see
also Figure 5). AGND_ADC1 is then connected to GND
(AGND_ADC signal) through a ferrite bead (E2).
V1P
VM
AGND_ADC
AGND_ADC
AGND_ADC
V2P
E5
E4
V1P_IN
V2P_IN
TP14
TP15
ADE7903
R1
330kΩ
R5
330kΩ
R10
330kΩ
R12
1kΩ
R2
330kΩ
R6
330kΩ
R11
330kΩ
R14
1kΩ
C11
33nF
C9
33nF
R13
1kΩ
C10
33nF
D4
D1
D9
D7
D10
D8
D5
D2
12927-
006
PHASE
ADE7903
9
8
10
VDD
GND
GND
LDO
VREF
E2
TP11
1
2
GROUND
CONNECTION
BETWEEN PIN 2
AND PIN 10
INTERNAL TO
ADE7903
C4A
C1A
C5A
C6A
C13A C14A
AGND_ADC
AGND_ADC1
TO
PIN 19
VDD
C2A
TO
GND
12927-
007
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