UG-AD7175-2
EVAL-AD7175-2SDZ User Guide
EVALUATION BOARD HARDWARE
DEVICE DESCRIPTION
The
is a highly accurate, high resolution, multiplexed,
2-/4-channel (fully differential/single-ended) Σ-Δ ADC. The
has a maximum channel-to-channel scan rate of
50 kSPS (20 µs) for fully settled data The output data rates range
from 5 SPS to 250 kSPS. The device includes integrated rail to
rail analog input and reference input buffers, an integrated
precision 2.5 V reference, and an integrated oscillator.
See the
data sheet for complete specifications.
Consult the data sheet in conjunction with this user guide when
using the evaluation board. Full details for the
are available on the Analog Devices website.
HARDWARE LINK OPTIONS
See Table 1 for default link options. By default, the board is
configured to operate from the supplied 9 V ac-to-dc adapter
connected to connector J5. The 5 V supply required for the
comes from the on-board low dropout regulator
(LDO). The
, with a 5 V output voltage, receives its
input voltage from J3 or J5 (depending on the position of LK2)
and generates a 5 V output.
Table 1. Default Link and Solder Link Options
Link
Default Option
Description
LK1
A
Selects the voltage applied to the power supply sequencer circuit (U3); dependent on AVDD1. Place in
Position A if using 5 V AVDD1, or Position B if using 2.5 V AVDD1.
LK2
B
Selects the external power supply from Connector J3 (Position A), or J4 (Position B).
LK5 to LK9
Inserted
Inserting these links sets up the on-board noise test. In this mode, all inputs short to the common
voltage via SL11.
SL1
A
Sets the voltage applied to the AVDD2 pin. Operates using the AVDD1 supply (default). Position B sets
the AVDD2 voltage to 3.3 V supply from the
(3.3 V) (U10) regulator.
SL2
A
Selects between an external or on-board AVDD1 source. Supplies AVDD1 from the
(5 V) (U7)
(default).
SL3
A
Selects between an external or on-board AVSS source. Supplies AVSS from the
(-2.5 V) (U4) (default).
SL4
A
Connects AIN4 to: A4 / J6 (Position A), REFOUT pin on the
(Position B) or AVSS (Position C).
Positions B and C are used to simplify using a single ended input source.
SL5
B
Selects between an external or on-board IOVDD source. Supplies IOVDD from the
(3.3 V) (U10)
(default). The evaluation board operates with a 3.3 V logic.
SL8
A
Routes A0 to: AIN0 pin on the
(Position A), Buffer/Inamp U8 (Position B), Funnel Amp U9 with
gain of 0.8x (Position C) or J10-1 (Position D).
SL9
A
Routes A2 to: AIN2 pin on the
(Position A), Buffer U12 (Position B) or Funnel Amp U9 gain of
0.4x (Position C).
SL10
A
Routes A3 to: AIN3 pin on the
(Position A), Buffer U12 (Position B) or Funnel Amp U9 gain of
0.4x (Position C).
SL11
A
Routes A1 to: AIN1 pin on the
(Position A), Buffer/Inamp U8 (Position B), Funnel Amp U9 with
gain of 0.8x (Position C) or J10-7 (Position D).
R49 to R51
Inserted
Connects AVSS and AGND for single-supply operation. To operate in split supply mode, remove these links.
Rev. Pr.C | Page 4 of 12
