Analog Devices EVAL-AD1940EB, Manual

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EVAL-AD1940EB/AD1941EB
Rev. 0 | Page 8 of 32
TYPICAL SETUPS
6-CHANNEL ANALOG INPUT/ OUTPUT
Input comes from the 6-channel analog inputs to the AD1940/
AD1941 SDATA_IN0 pin, SDATA_IN1 pin, and SDATA_IN2
pin, and outputs on whichever outputs (SDATA_OUTx) are
designed in the SigmaStudio software. Default outputs for the
input are SDATA_OUT0, SDATA_OUT1, and SDATA_OUT2,
or Analog Output 0 to Analog Output 5.
In this setup, the AD1939’s oscillator connected to a
12.288 MHz crystal generates the master clock. The AD1871 is
the serial data clock master, and the AD1939’s and AD1940/
AD1941’s serial data ports are slaves. Table 6 explains how the
switches and jumpers need to be set up for this mode. Any
component setting not mentioned in this table can be
considered as “don’t care.”
Table 6. Evaluation Board Settings for Analog I/O
Component Setting
SW2 Position 1
SW9 Position 0
LK1 Disconnected
LK2/LK3 Connected
LK5/LK14 AD1939
J24 Line
S1
Position 2 up (1), all other positions down (0)
S/PDIF INPUT/ANALOG AND S/PDIF OUTPUT
Input comes from the stereo S/PDIF receiver to the
AD1940/AD1941 SDATA_IN0 pin and outputs on whichever
outputs (SDATA_OUTx) are designed in the SigmaStudio
software. Default outputs for the input are SDATA_OUT0, or
Analog Output 0 or Analog Output 1. SDATA_OUT0 is also
sent to the S/PDIF transmitter.
In this setup, the master clock and serial data clocks are generated
by the CS8414. Table 7 explains how the switches and jumpers
need to be set up for this mode. Any component setting not
mentioned in this table can be considered as “don’t care.”
Table 7. Evaluation Board Settings for S/PDIF Input/Analog
and S/PDIF Output
Component Setting
SW2 Position 0
SW9 Position 0
LK1 Connected
LK2/LK3 Disconnected
LK5/LK14 S/PDIF
SW10
Selects S/PDIF source from either optical or RCA
S1 Position 2 up (1), all other positions down (0)
SERIAL DATA INPUT/OUTPUT
This mode is intended to be used to connect to external devices,
such as ADCs, DACs, or compressed audio (such as AC-3)
decoders. Input comes from the external Input Header J11 and
feeds the AD1940/AD1941 SDATA_IN0 pin, SDATA_IN1 pin,
SDATA_IN2 pin, and SDATA_IN3 pin. Output is on Output
Header J7 and Output Header J8. The specific output pins
(SDATA_OUTx) are designated in the SigmaStudio software.
The signals on these headers are directly connected to the
AD1940/AD1941 using I
2
S, left-justified, or right-justified
modes. Default outputs for the input are SDATA_OUT0,
SDATA_OUT1, SDATA_OUT2, and SDATA_OUT3, or Analog
Output 0 to Analog Output 5. If the master clock is to be output
on Output Header J7, a second jumper needs to be placed on
Jumper LK5/LK14 at Position Intf-Out0. For the master clock to
be output on Output Header J8, an additional jumper must be
placed in Position Intf-Out. In order to avoid multiple clocks
driving the MCLK line, ensure that SW6 to SW8 are set
properly before placing these jumpers.
In this setup, the master clock and serial data clocks are
generated by the external source.
Table 8 explains how the switches and jumpers need to be set up
for this mode. Any component setting not mentioned in this
table can be considered as “don’t care.”
Table 8. Evaluation Board Settings for Serial Data I/O
Component Setting
SW2 Position 5
SW9 Position 0
LK1 Connected
LK2/LK3 Disconnected
LK5/LK14 Intf-In
SW6 In
(down)
SW7 Out (right), if the master clock is to be output on
the serial data headers
SW8
Out (left), if the master clock is to be output on
the serial data headers
S1 Position 2 up (1), all other positions down (0)