5
Rev. 0
Figure 5. Efficiency vs Load Current
Figure 6. Load Step Response
f
SW
= 2MHz
V
IN
= 3.3V
4-PHASE
3-PHASE
2-PHASE
LOAD CURRENT (A)
0
10
20
30
40
50
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
dc3186a F04
10A
20A
V
IN
= 3.3V
5µs/DIV
I
LOAD
5A/DIV
V
OUT
50mV/DIV
dc3186a F05
TYPICAL PERFORMANCE CHARACTERISTICS
THEORY OF OPERATION
Introduction to the DC3186A
The DC3186A demonstration circuit features the LTC3311,
an automotive grade low voltage synchronous step-down
Silent Switcher in a two, three, or four phase operation.
The LTC3311 is a monolithic, constant frequency, current
mode step-down DC/DC converter. Connecting the RT pin
of the master phase with a resistor to AGND programs
the frequency from 500kHz to 5MHz. With R
T
resistor
on master phase, the MODE/SYNC pin becomes a clock
output to drive the MODE/SYNC pins of the slave phases.
The DC3186A can operate with an external clock by short-
ing the master phase RT pin to VIN with a 0Ω resistor in
the R5 location and applying a clock signal on the MODE/
SYNC turret. If the EN pin is low, the LTC3311 is in shut-
down and in a low quiescent current state. When the EN
pin is above its threshold, the switching regulator will be
enabled.
Connecting the FB pin to VIN configures a phase as a
slave. The MODE/SYNC pin becomes an input, and the
voltage control loop is disabled. The current control loop
in the slave phase is still active, and the peak current
is controlled via the shared ITH node. The phasing of a
slave phase relative to the master phase is programmed
with a resistor divider on the RT pin. Refer to Table 5 of
the data sheet for more information on setting the slave
phase angle.
In the multiphase application, the LTC3311 operates in
forced continuous mode. At light loads, the slave phases
will continue to operate in forced continuous mode.
Setting the compensation for the multiphase is similar
to setting the compensation to the single phase. When
designing the compensation network, controlling the loop
stability and transient response are the two main con-
siderations. The LTC3311 has been designed to operate
at a high bandwidth for fast transient response capabili-
ties. This reduces output capacitance required to meet
the desired transient voltage range. The mid-band gain
of the loop increases with R8 and the bandwidth of the
loop increases with decreasing C14. C11 along with R6
provides a phase lead which will improve the phase mar-
gin. C13, C33, C34, and C44 along with R8 provides a
high frequency pole to reduce the high frequency gain.
C13, C33, C34, and C44 are in parallel on the ITH node.
The sum of these caps will be the total capacitance on the
master phase ITH pin. Too much capacitance will slow
down the response time.
Loop stability is generally measured using the Bode Plot
method of plotting loop gain in dB and phase shift in
degrees. The 0dB crossover frequency should be less
the 1/6 of the operating frequency to reduce the effects
of added phase shift of the modulator. The control loop
phase margin goal should be 45° or greater and a gain
