Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 1-23
Introduction
Dynamic Power Management
The processor provides four operating modes, each with a different perfor-
mance/power profile. In addition, dynamic power management provides
the control functions to dynamically alter the processor core supply volt-
age to further reduce power dissipation. Control of clocking to each of the
peripherals also reduces power consumption.
Full On Mode (Maximum Performance)
In the full on mode, the PLL is enabled, not bypassed, providing the max-
imum operational frequency. This is the normal execution state in which
maximum performance can be achieved. The processor core and all
enabled peripherals run at full speed.
Active Mode (Moderate Power Savings)
In the active mode, the PLL is enabled, but bypassed. Because the PLL is
bypassed, the processor’s core clock (
CCLK
) and system clock (
SCLK
) run at
the input clock (
CLKIN
) frequency. In this mode, the
CLKIN
to
VCO
multi-
plier ratio can be changed, although the changes are not realized until the
full on mode is entered. DMA access is available to appropriately config-
ured L1 memories.
In the active mode, it is possible to disable the PLL through the PLL con-
trol register (
PLL_CTL
). If disabled, the PLL must be re-enabled before
transitioning to the full on or sleep modes.
Sleep Mode (High Power Savings)
The sleep mode reduces power dissipation by disabling the clock to the
processor core (
CCLK
). The PLL and system clock (
SCLK
), however, con-
tinue to operate in this mode. Typically an external event or RTC activity
will wake up the processor. When in the sleep mode, assertion of any