Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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Description of Operation
13-8 ADSP-BF537 Blackfin Processor Hardware Reference
each start bit, so the error accumulates only over the length of a single
word. A receive filter removes spurious pulses of less than two times the
sampling clock period.
IrDA Transmit Operation
To generate the IrDA pulse transmitted by the UART, the normal NRZ
output of the transmitter is first inverted if the
TPOLC
bit is cleared, so a 0
is transmitted as a high pulse of 16 UART clock periods and a 1 is trans-
mitted as a low pulse for 16 UART clock periods. The leading edge of the
pulse is then delayed by six UART clock periods. Similarly, the trailing
edge of the pulse is truncated by eight UART clock periods. This results in
the final representation of the original 0 as a high pulse of only 3/16 clock
periods in a 16-cycle UART clock period. The pulse is centered around
the middle of the bit time, as shown in
Figure 13-3 . The final IrDA pulse
is fed to the off-chip infrared driver.
This modulation approach ensures a pulse width output from the UART
of three cycles high out of every 16 UART clock cycles. As shown in
Table 13-1 on page 13-12 , the error terms associated with the bit rate gen-
erator are very small and well within the tolerance of most infrared
transceiver specifications.
Figure 13-3. IrDA Transmit Pulse
0
1 0
8/16
9/16
7/16
16/16
NRZ
INVERTED
FINAL
IrDA
8/16
9/16 7/16
16/16