Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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SPORT Registers
12-62 ADSP-BF537 Blackfin Processor Hardware Reference
into the RX hold registers for primary and secondary data, respectively.
Data from the hold registers is moved into the FIFO based on
RXSE
and
SLEN
.
The SPORT RX interrupt is generated when
RSPEN = 1
and the RX FIFO
has received words in it. When the core processor has read all the words in
the FIFO, the RX interrupt is cleared. The SPORT RX interrupt is set
only if SPORT RX DMA is disabled; otherwise, the FIFO is read by
DMA reads.
If the program causes the core processor to attempt a read from an empty
RX FIFO, old data is read, the
RUVF
flag is set in the
SPORTx_STAT
register,
and the SPORT error interrupt is asserted. The
RUVF
bit is a sticky bit and
is cleared only when the SPORT is disabled. To determine if the core can
access the RX registers without causing this error, first read the RX FIFO
status (
RXNE
in the SPORTx status register). The
RUVF
status bit is updated
even when the SPORT is disabled.
The
ROVF
status bit is set in the
SPORTx_STAT
register when a new word is
assembled in the RX shift register and the RX hold register has not moved
the data to the FIFO. The previously written word in the hold register is
overwritten. The
ROVF
bit is a sticky bit; it is only cleared by disabling the
SPORT RX.
Figure 12-32. SPORTx Receive Data Register
SPORTx Receive Data Register (SPORTx_RX)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Receive Data[31:16]
Reset = 0x0000 0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Receive Data[15:0]
SPORT0:
0xFFC0 0818
SPORT1:
0xFFC0 0918