Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 6-49
External Bus Interface Unit
Mode Register Set Command
The Mode Register Set (MRS) command initializes SDRAM operation
parameters. This command is a part of the SDRAM powerup sequence.
The MRS command uses the address bus of the SDRAM as data input.
The powerup sequence is initiated by writing 1 to the
PSSE
bit in the
SDRAM memory global control register (
EBIU_SDGCTL
) and then writing
or reading from any enabled address within the SDRAM address space to
trigger the powerup sequence. The exact order of the powerup sequence is
determined by the
PSM
bit of the
EBIU_SDGCTL
register.
The MRS command initializes these parameters:
• Burst length = 1, bits
A[2–0]
, always 0
• Burst type = sequential, bit
A[3]
, always 0
• CAS latency, bits
A[6–4]
, programmable in the
EBIU_SDGCTL
register
• Bits
A[12–7]
, always 0
After powerup and before executing a read or write to the SDRAM mem-
ory space, the application must trigger the SDC to write the SDRAM’s
mode register. The write of the SDRAM’s mode register is triggered by
writing a 1 to the
PSSE
bit in the SDRAM memory global control register
(
EBIU_SDGCTL
) and then issuing a read or write transfer to the SDRAM
address space. The initial read or write triggers the SDRAM powerup
NOP High High Low High High High Don’t
care Don’t care
Inhibit High High High Don’t
care Don’t
Care Don’t
care Don’t
care Don’t care
Table 6-11. Pin State During SDC Commands (Cont’d)
Command SCKE
(n - 1) SCKE
(n) SMS SRAS SCAS SWE SA10 Addresses