Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 6-43
External Bus Interface Unit
Multibank Operation
Since an SDRAM contains 4 independent internal banks (A-D), the SDC
is capable of supporting multibank operation thus taking advantage of the
architecture.
Any first access to SDRAM bank (A) will force an activate command
before a read or write command. However, if any new access falls into the
address space of the other banks (B, C, D) the SDC leaves bank (A) open
and activates any of the other banks (B, C, D). Bank (A) to bank (B)
active time is controlled by t
RRD
= t
RCD
+ 1. This scenario is repeated
until all 4 banks (A-D) are opened and results in an effective page size up
to 4 pages because no latency causes switching between these open pages
(compared to 1 page in only one bank at the time). Any access to any
closed page in any opened bank (A-D) forces a precharge command only
to that bank. If, for example, 2 MemDMA channels are pointing to the
same internal SDRAM bank, this always forces precharge and activation
cycles to switch between the different pages. However, if the 2 MemDMA
channels are pointing to different internal SDRAM banks, it does not
cause additional overhead. See
Figure 6-11 .
L
The benefit of multibank operation reduces precharge and activa-
tion cycles by mapping opcode/data among different internal
SDRAM banks driven by the
A[19:18]
pins.