Blackfin A-V EZ-Extender Manual
2-13
A-V EZ-Extender Hardware Reference
PPI0_SYNC2 Direction Setup Jumper (JP6.2/4/6)
The direction of the
PPI0_SYNC2
signal can be either fixed or programmed,
depending on the state of a general-purpose flag.
set the
PPI0_SYNC2
direction.
I
2
S Enable Jumper (JP7.1/2)
When
JP7.1/2
is installed, the SPORT signals are routed for I
2
S SPORT
communication protocol mode. To accomplish this, the receive and trans-
mit clocks of the processor are driven by the output clock of the
AD1836A audio codec. The same is done for the frame sync signals.
SPORT Data Connect Jumpers (JP7.3/4, JP7.5/6)
The
JP7.3/4
and
JP7.5/6
jumpers connect data output pins (
ASDATA1
and
ASDATA2
) of the audio codec to the primary and secondary SPORT data
input pins of the processor. The audio codec is driving these pins; with the
help of the
JP7.3/4
and
JP7.5/6
jumpers, the processor’s pins can be
re-used when the codec is disabled.
Table 2-8. Setting Direction of PPI0_SYNC2 (JP6.2/4/6)
Jumper Location
PPI0_SYNC2 Direction
JP6.2/4
Controlled by a flag pin
JP6.4/6
Input to the processor
Uninstalled
Output from the processor
