Analog Devices ADV8005, Hardware Reference Manual

Page: 52 / 317

UG-707 ADV8005 Hardware Reference Manual
mas_vs_ie , IO Map, Address 0x1BD4[0]
This bit is used to control the input path enable for the master VS pin.
Function
mas_vs_ie Description
0 (default) input path disable
1 input path enable
2.2.2.5. Serial Video Rx
The Serial Video Rx can only be connected to the RX input channel (see Section 2.2.2.8 ).
2.2.2.6. Primary Input Channel
The ADV8005 primary input channel incorporates an input formatter, CSC, updither block and ACE control.
The input formatter provides a number of controls to configure what data the video TTL input channel is configured for. The video TTL input
channel must be connected to either the video TTL input pins, the EXOSD TTL input pins or the high speed TTL input pins using
p_inp_chan_sel[1:0] . If the primary input channel is connected to the video TTL input pins, the format and bit width of the data, for example,
2 x 8 bit buses of 4:2:2 data, must be specified using vid_format_sel[4:0] . vid_swap_bus_ctrl[2:0] can be used to indicate which input pins are
used to carry the upper, middle and lower ranges of bits (for example, upper = D[35:25], middle = D[24:12], lower = D[11:0] or upper = D[11:0],
middle = D[35:25], lower = D[24:12]).
p_inp_chan_sel[1:0] , IO Map, Address 0x1A07[1:0]
This signal is used to select the input for the Primary Input Channel.
Function
p_inp_chan_sel[1:0] Description
00 (default) Video TTL input (P[35:0])
01 EXOSD TTL Input (OSD_IN[23:0])
10 48-bit TTL input (OSD_IN[11:0] and P[35:0]) for 3GHz interleaved TTL
11 Reserved
vid_format_sel[4:0] , IO Map, Address 0x1B48[4:0]
This signal is used to select the input format for the video data.
Function
vid_format_sel[4:0] Description
0x00 1 x 8-bit bus, SDR 4:2:2
0x01 1 x 10-bit bus, SDR 4:2:2
0x02 1 x 12-bit bus, SDR 4:2:2
0x03 2 x 8-bit buses, SDR 4:2:2
0x04 2 x 10-bit buses, SDR 4:2:2
0x05 2 x 12-bit buses, SDR 4:2:2
0x06 3 x 8-bit buses, SDR 4:4:4 (P[35:28], P[23:16], P[11:4])
0x07 3 x 10-bit buses, SDR 4:4:4 (P[35:26], P[23:14], P[11:2])
0x08 (default) 3 x 12-bit buses, SDR 4:4:4
0x09 1 x 8-bit bus, DDR 4:2:2
0x0A 1 x 10-bit bus DDR 4:2:2
0x0B 1 x 12 bit bus, DDR 4:2:2
0x0C 3 x 8 bit buses, SDR 4:4:4 (P[23:0])
0x0D 2 x 3 x 8-bit interleaved buses, SDR 4:4:4
0x0E 2 x 2 x 8-bit interleaved buses, SDR 4:2:2
0x0F 2 x 2 x 10-bit interleaved buses, SDR 4:2:2
0x10 2 x 2 x 12-bit interleaved buses, SDR 4:2:2
0x11 3 x 10-bit buses, SDR 4:4:4 (P[29:0])
0x12 3 x 7-bit buses, SDR 4:4:4 (for external alpha blend)
0x13 3 x 10-bit buses, SDR 4:4:4 (OSD_IN[23:0] and P[35:30])
Rev. A | Page 52 of 317