Analog Devices ADV8005, Hardware Reference Manual

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ADV8005 Hardware Reference Manual UG-707
47 Ω series termination resistors should be placed in the middle of the trace on the following signals:
•
Data bus signals – DDR_DQ31-DDR_DQ0
•
Data strobe signals – DDR_DQS3 DDR_DQS3B-DDR_DQS0 DDR_DQS0B
The DDR2 reference voltage (DDR_VREF) should be routed as far away as possible from other signals to avoid any variations on the voltage.
This trace should be wide. There should be a 100 nF decoupling cap close to the DDR2 reference voltage pins as well as the
ADV8005 reference pin.
Power Supply Bypassing
It is recommended to bypass each power supply pin with a 0.1 uF and a 10 nF capacitor where possible. The fundamental idea is to have a bypass
capacitor within 0.5 cm of each power pin.
Current should flow from the power plane to the capacitor to the power pin. The power connection should not be made between the capacitor
and the power pin. Generally, the best approach is to place a via underneath the 10 nF capacitor pads down to the power plane (refer to
Figure 143 ).
Figure 143: Recommended Power Supply Decoupling
It is recommended to individually filter all supplies to prevent switching noise on some supplies coupling onto other more sensitive supplies.
For example, DVDD consumes a significant amount of current and will also suffer significant switching noise. DVDD must be isolated from
more sensitive supplies such as PVDD3, PVDD5 and PVDD6.
The DVDD and DVDD_DDR supplies should be connected to the same supply – PVDD_DDR should be filtered from DVDD to provide a
noise free power supply.
It is recommended to use a single ground plane for the
ADV8005 . Careful attention must be paid to the layout of any internal power supply
planes when traces run on adjacent layers – traces on a layer directly above or below a power supply layer must not cross between two power
supply planes as this will impact the return current paths.
General Digital Inputs and Outputs
The trace length that the digital inputs/outputs have to sink/source should be minimized. Longer traces have higher capacitance, which requires
more current that can cause more internal digital noise. Shorter traces reduce the possibility of reflections. It is recommended to route traces in
the shortest trace length possible and keep the number of layer transitions to a minimum.
If possible, the digital output driver capacitance loading should be limited to less than 15 pF. This can be accomplished easily by keeping traces
short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside
the
ADV8005 , creating more digital noise on its power supplies.
Particular attention must be paid to the routing of clock and sync signals, for example, PCLK, OSD_CLK, HS, OSD_HS, VS, OSD_VS, DE,
OSD_DE, XTALN, and XTALP. Any noise that gets onto these signals can add jitter to the system. Therefore, the trace length should be
minimized, and digital or other high frequency traces should not be run near it.
XTAL and Load Cap Value Selection
The ADV8005 requires a 27 MHz crystal. Figure 144 shows an example of a reference clock circuit for the ADV8005 . Special care must be taken
when using a crystal circuit to generate the reference clock for the ADV8005 . Small variations in reference clock frequency can impair the
performance of the ADV8005 .
10nF 0.1uF
via to GND layer
and GND pin
via to VDD pin VDD supply
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