UG-707
ADV8005 Hardware Reference Manual
3.3.3.5.
Progressive to Interlaced Converter in SVSP
The PtoI converter block in the SVSP is used to convert progressive video to interlaced video. It drops odd or even lines of the progressive video
based on the output interlaced video field signal. Support is limited to 480p and 576p. The associated interlaced timing signals can be generated
in the PtoI hardware block.
The PtoI converter in the SVSP cannot operate in standalone mode – it must be connected to the SVSP.
The PtoI hardware can be enabled using
svsp_p2i_enable
, Secondary VSP Map,
Address 0xE649[5]
This bit is used to enable the PtoI in Secondary VSP.
Function
svsp_p2i_enable
Description
0 (default)
Disable
1
Enable
The input video to the PtoI block is defined using
. For more details on the values which must be programmed into this
register, refer to
svsp_p2i_vid[7:0]
, Secondary VSP Map,
Address 0xE64A[7:0]
'This register is used to set the VIC of the PtoI in Secondary VSP.
Function
svsp_p2i_vid[7:0]
Description
0x00 (default)
Default
Table 32: VID for PtoI
Input Timing Format to
P2I
576p
480p
svsp_s_p2i_vid
17
2
3.4.
VSP REGISTER ACCESS PROTOCOLS
This section is used to describe the methods available to the user to update the VSP registers. The following types of register access protocols are
available:
•
Bootup protocol
•
Reboot protocol
•
Gentle reboot protocol
•
VOM set protocol
•
Free access protocol
These protocols are recommended to the user as best practice for updating VSP registers. The appropriate protocol should be used depending
on the current status of the device. The seamless transfer of the VSP between standards can be achieved by using the bootup protocol, reboot
protocol, gentle reboot protocol and VOM set protocols. If not changing VSP registers in real time, the free access protocol can be used.
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