Analog Devices ADuCM320, Hardware Reference Manual

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ADuCM320 Hardware Reference Manual UG-498
Rev. C | Page 37 of 196
IDACs
IDAC FEATURES
The ADuCM320 provides four IDACs. These are low noise, low drift current source outputs.

IDAC0, IDAC1, IDAC2 and IDAC3: 0 mA to 150 mA full-scale output, bias current setting for optical laser.
IDAC BLOCK DIAGRAM
3.3V
2.5V OUT
AGND
LDO
1.2V
VREF
3.16 k Ω
R
REF
5ppm
0.1%
PGND PGND
PGND
PGND ADC
INPUT
MUX
PVDD PVDD
CDAMP
10nF
11-BIT
IDAC
5-BIT
IDAC
BUF
BUF
PULL-DOWN
100 µA
SINK
CURRENT
IDAC3
1117
6-
008
Figure 9. Example IDAC Circuit—IDAC3
IDAC OVERVIEW
Precision Current Generation and Fault Protection
The reference current for the IDACs is generated by a precision internal band gap voltage reference (V
BANDGAP
)) and an external precision
resistor (R
REF
, 5 ppm, 0.1%). The reference current is equal to V
BANDGAP
÷ R
REF
. The band gap voltage reference is a low drift, high accuracy
voltage source that helps to minimize the overall IDAC gain error and gain error drift. The noise of the IDAC outputs is limited by the
low-pass filter on the output stage; each IDAC requires a 10 nF capacitor between PVDD and its CDAMP pin.
Figure 9 shows the typical architecture of the IDAC. The parallel 11-bit and 5-bit IDACs set the output current. The output of these
IDACs are summed together and fed to a current mirror and then are gained up at the output stage.
Production trimming of the LDO band gap reference aids performance. In addition, gain trimming and scaling of the current mirror and
output stages are also included in the ATE test program.
IDAC Shutdown
IDAC0, IDAC1, IDAC2, and IDAC3 also have a small current sink capability to minimize the offset current when the data register is set
to 0. The IDACxCON[1] bit can be used to enable a pull-down current source to PGND. This pull-down current is typically 100 μA.
IDAC Output Filter
Each IDAC has a filter on the output stage to minimize noise. Each IDAC requires an external 10 nF capacitor between PVDD and its
CDAMP pin as per the
ADuCM320 data sheet. The on-chip, programmable resistor is controlled by the IDACxCON[5:2] bits.
Table 26. IDAC Filter Bandwidth Control Settings
IDACxCON[5:2] R Value Cutoff Frequency (f
C
)
0000 60 Ω 262 kHz
0101 5.6 kΩ 2.8 kHz
0110 11.2 kΩ 1.4 kHz
0111 22.2 kΩ 715 Hz
1000 44.4 kΩ 357 Hz
1001 104 kΩ 153 Hz
All other options are reserved