Analog Devices ADuCM310, Hardware Reference Manual

Page: 166 / 192

UG-549 ADuCM310 Hardware Reference Manual
Rev. C | Page 166 of 192
REGISTER SUMMARY: GENERAL-PURPOSE TIMER 2
Table 240. Timer 2 Register Summary
Address Name Description Reset RW
0x40000800 T2LD 16-bit load value register 0x0000 RW
0x40000804 T2VAL 16-bit timer value register 0x0000 R
0x40000808 T2CON Control register 0x000A RW
0x4000080C T2CLRI Clear interrupt register 0x0000 W
0x40000810 T2CAP Capture register 0x0000 R
0x4000081C T2STA Status register 0x0000 R
REGISTER DETAILS: GENERAL-PURPOSE TIMER 2
16-Bit Load Value Register
Address: 0x40000800, Reset: 0x0000, Name: T2LD
Table 241. Bit Descriptions for T2LD
Bits Bit Name Description Reset Access
[15:0] LOAD Load value. The up/down counter is periodically loaded with this value if
periodic mode is selected (T2CON[3] = 1). LOAD writes during up/down
counter timeout events are delayed until the event has passed.
0x0 RW
16-Bit Timer Value Register
Address: 0x40000804, Reset: 0x0000, Name: T2VAL
Table 242. Bit Descriptions for T2VAL
Bits Bit Name Description Reset Access
[15:0] VAL Current count. Reflects the current up/down counter value. Value delayed
two PCLK cycles due to clock synchronizers. 0x0 R
Control Register
Address: 0x40000808, Reset: 0x000A, Name: T2CON
Table 243. Bit Descriptions for T2CON
Bits Bit Name Description Reset Access
[15:13] RESERVED Reserved. 0x0 R
12 EVENTEN Event select. This bit enables and disables the capture of events. Used in
conjunction with the EVENT select range: when a selected event occurs
the current value of the up/down counter is captured in T2CAP.
0x0 RW
0: events are not captured.
1: events are captured.
[11:8] EVENT Event select range. Timer event select range (0 to 15). 0x0 RW
7 RLD Reload control. RLD is only used for periodic mode; this bit allows the user
to select whether the up/down counter is reset only on a timeout event or
also when T2CLRI[0] is set.
0x0 RW
1: up/down counter is reset when T2CLRI[0] is set.
0: up/down counter is only reset on a timeout event.
[6:5] CLK Clock select. These bits select a timer clock from the four available clock
sources. 0x0 RW
00: PCLK.
01: HCLK.
10: LFOSC, 32 kHz oscillator.
11: HFXTAL, if CLKCON0[11] = 1.
11: HFOSC, if CLKCON0[11] = 0.