Analog Devices ADuC7026 Reference Manual Download Page 5

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–4–

AN-744

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AN-744

EXTERNAL MEMORY INTERFACE

A footprint for a 32 kB



16 SRAM is provided on board

as well as a footprint for a 16-bit D-latch since address
and data are multiplexed on the external bus.
The memory footprint is for a CY7C1020CV33 and the
latch footprint is for a 74LVT16373AGG.
Note  that  you  can  use  different  versions  of  the
CY7C1020CV33  memory,  with  different  access  times.
Wait  states  can  be  added  in  the  XMxPAR  register  to
allow interfacing a slower memory if required.

Connections

Controls:

, and AE are the minimum control

signals of any memory interface.

MSO

, memory select is connected to

enable the memory only when necessary.

BHE

and

BLE

allow the user to select the high

or low byte of the 16-bit memory.

Data:

16 bits of data AD[15-0] are directly con-
nected from the ADuC7026 to the memory.

Addresses:

To address 32 kB, only a 14-bit address is
required.
There are two ways of addressing a 16-bit
memory:

1. Connecting AD[14-0] to A[14-0]. To enable

it requires dynamic addressing (set Bit 11
in XMxPAR) to address in 16 -bit mode
instead of 8-bit mode.

2. Connecting AD[15-1] of the ADuC702x to

A[14-0] of the memory, without using
dynamic addressing.

On the evaluation board, AD[14-0] are
connected. In software, dynamic addressing
must be enabled.

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Figure 2. External Memory Connections

REV. 0

Summary of Contents for ADuC7026

Page 1: ...ctly to the digital section and is filtered before being routed into the analog section of the board FEATURES Power Supply The user should connect the 9 V power supply via the 2 1 mm input power socke...

Page 2: ...external components as required in the user s application As can be seen from the layout AVDD AGND VDDIO and DGND tracks are provided in this prototype area External Memory and Latch Footprint Footpr...

Page 3: ...C1 output to D1 Slide S1 7 to the off position to use DAC1 output on J3 header EXTERNAL CONNECTORS J3 Analog I O Connector The analog I O connector J3 provides external connections for all ADC inputs...

Page 4: ...2 18 P2 7 PWM1L MS3 J2 19 P3 7 PWMSYNC AD7 PLAI 15 J2 20 P3 6 PWMTRIP AD6 PLAI 14 J2 21 P0 7 ECLK SIN PLAO 4 Pin Number Pin Description J2 22 P2 0 CONV SOUT PLAO 5 J2 23 P0 5 IRQ1 ADCBUSY MS0 PLAO 2 J...

Page 5: ...any memory interface MSO memory select is connected to CE to enable the memory only when necessary BHE and BLE allow the user to select the high or low byte of the 16 bit memory Data 16 bits of data A...

Page 6: ...e sample code in adc pot c the variation in the potentiometer resistance can be seen on the output LED Note that the internal and external references are 2 5 V which gives an ADC input range of 0 V to...

Page 7: ...7 AN 744 SCHEMATIC Figure 4 ADuC7026 Evaluation Board Schematic REV 0...

Page 8: ...8 AN 744 Figure 5 ADuC7026 Evaluation Board Silkscreen REV 0...

Page 9: ...tch D1 D2 D3 3 LED 1 8 mm miniature LED 515 620 Farnell D4 1 PRLL4002 Diode BAV103DITR ND Digi Key C1 C5 C13 C15 C18 C22 C23 7 10 F Surface mount tantalum cap 197 130 Farnell Taj B case C2 C4 C6 C12 C...

Page 10: ...R21 R22 R24 3 100 k Surface mount resistor 911 471 Farnell 0603 case L1 1 Ferrite bead Surface mount inductor 581 094 Farnell 1206 case J1 1 4 pin header 4 pin 90 single row header TSM 104 02 T SH Sa...

Page 11: ...11...

Page 12: ...respective owners Purchase of licensed I2 C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2 C Patent Rights to use...

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