ADSP-BF526 EZ-Board Evaluation System Manual
2-5
ADSP-BF526 EZ-Board Hardware Reference
Table 2-2. PG Port Programmable Flag Connections
Processor Pin
Other Processor Function
EZ-Board Function
PG0
HWAIT
Default:
PB1
via
SW21.1
and
RN5
.
UART1
CTS
(
HWAIT
) via
U32
,
SW14.1
, host connector
P9.12
,
CHG
GPIO
JP15.1
, expansion interface II
(
P2.37
,
P4.37
,
J1.52
), land grid array via
P7.B27
.
PG1
SPISS#/SPISEL1#
Default: SPI flash (
U6
) CS via
SW11.4
and
RN3
.
Expansion interface II (
P2.21
,
P4.21
,
P4.26
,
P2.26
),
land grid array via
P7.B26
.
PG2
SPISCK
Default: SPI flash (
U6
).
Expansion interface II (
P2.24
,
P4.24
), land grid array
via
P7.B9
.
PG3
SPIMISO/DR0SECA
Default: SPI flash (
U6
) via
RN3
.
Expansion interface II (
P2.16
,
P2.27
,
P4.27
), land
grid array via
P7.B23
.
PG4
SPIMOSI/DT0SECA
Default: SPI flash (
U6
).
Expansion interface II (
P2.15
,
P2.25
,
P4.25
), land
grid array via
P7.B24
.
PG5
TMR1/PPIFS2/TFS0A
Default:
PPIFS2
P3.14
.
Land grid array via
P7.B17
.
PG6
DT0PRIA/TMR2/PPIFS3
Default:
DT0PRIA
codec (
U31
) via
SW7.2
.
Expansion interface II (
P2.13
,
P3.15
), land grid array
via
P7.B18
.
PG7
TMR3/DR0PRIA/UART0TX
Default:
DR0PRIA
codec (
U31
) via
SW7.3
.
Expansion interface II (
P2.14
,
P2.31
,
P3.36
), land
grid array via
P7.B14
.
PG8
TMR4/RFS0A/UART0RX/
TACI4
Default:
RFS0A
codec (
U31
) via
SW7.4
.
Expansion interface II (
P3.35
,
P2.20
,
P2.32
), land
grid array via
P7.B15
.
PG9
TMR5/RSCLK0A/TACI5
Default:
RSCLK0A
codec (
U31
) via
SW2.2
.
Expansion interface II (
P2.18
,
P3.38
), land grid array
via
P7.B11
.
PG10
TMR6/TSCLK0A/TACI6
Default:
TSCLK0A
codec (
U31
) via
SW2.1
.
Expansion interface II
P2.17
, land grid array via
P7.B12
.