DAG Operations
4-10
ADSP-2126x SHARC Processor Hardware Reference
•
“Addressing With DAGs” on page 4-10
•
“Data Addressing Stalls” on page 4-12
•
“Addressing Circular Buffers” on page 4-12
•
“Modifying DAG Registers” on page 4-17
An important item to note from
is that the DAG automatically
adjusts the output address per the word size of the address location (short
word, normal word, or long word). This address adjustment lets internal
memory use the address directly.
SISD/SIMD mode, access word size, and data location (inter-
nal/external) all influence data access operations.
Addressing With DAGs
The DAGs support two types of modified addressing which is defined as
generating an address that is incremented by a value or a register. In
pre-modify addressing, the DAG adds an offset (modifier), which is either
an
M
register or an immediate value, to an
I
register and outputs the result-
ing address. Pre-modify addressing does not change or update the
I
register. The other type of modified addressing is post-modify addressing.
In post-modify addressing, the DAG outputs the
I
register value
unchanged, then adds an
M
register or immediate value, updating the
I
register value.
compares pre- and post-modify addressing.
The difference between pre-modify and post-modify instructions in the
DSP’s assembly syntax is the position of the index and modifier in the
instruction. If the
I
register comes before the modifier, the instruction is a
post-modify operation. If the modifier comes before the
I
register, the
instruction is a pre-modify without update operation. The following
instruction accesses the program memory location indicated by the value
in
I15
and writes the value
I15
+
M12
to the
I15
register:
R6 = PM(I15,M12); /* Post-modify addressing with update */
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...