Table 5-8
SDRAM pin connections
Pin Type
Description
CAS
I/O/Z
SDRAM Column Address Select pin. Connect to SDRAM’s CAS buffer pin.
DQM
O/Z
SDRAM Data Mask pin. Connect to SDRAM’s DQM buffer pin.
The processor drives this pin high during reset, until SDRAM is started.
MSx
O/Z
Memory select lines of external memory bank configured for SDRAM. Connect to
SDRAM’s
CS (chip select) pin.
RAS
I/O/Z
SDRAM Row Address Select pin. Connect to SDRAM’s RAS pin.
SDA10
O/Z
SDRAM A10 pin. SDRAM interface uses this pin to retain control of the SDRAM device
during host bus requests. Connect to SDRAM’s A10 pin.
SDCKE
I/O/Z
SDRAM Clock Enable pin. Connect to SDRAM’s CKE pin.
SDCLK0
O/S/Z
SDRAM SDCLK0 output pin. Connect to the SDRAM’s CLK pin.
SDCLK1
O/S/Z
SDRAM SDCLK1 output pin. Connect to the SDRAM’s CLK pin.
SDWE
I/O/Z
SDRAM Write Enable pin. Connect to SDRAM’s WE or W buffer pin.
I = Input; O = Output; S = Synchronous; Z = Hi-Z
There are two 1M x 16 bit SDRAM chips on the EZ-KIT Lite board connected to MS3. They are
configured to be accessed in parallel, providing 1M x 32 bits of external data memory, starting at address
0x3000000. The ADSP-21065L uses address line 13 as the bank select. Additionally, the ADSP-
21065L has a separate address line (line 10) for the SDRAM, since this line is used during refresh. This
allows refresh to occur while another data transfer runs on the data bus.
See Chapter 10, “SDRAM Interface” in the
ADSP-21065L SHARC User’s Manual
for more information
on the SDRAM controller.
5.11 Timing Diagrams
Figure 5-5 EMAFE Write Cycle Timing Parameter Definitions
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