Preliminary Technical
Data
Rev. PrA | Page 3 of 82
DIGITAL PRE-DISTORTION
This section provides an overview of the digital pre-distortion (DPD) function provided in the transceiver, including a hardware
architecture overview, an overview of the DPD algorithm with references to features that enhance DPD robustness and
performance in dynamic signaling conditions, and a summary of API software interface functions to configure these DPD
functions. DPD enables users to achieve higher power amplifier (PA) efficiency by extending the linear operating region of the
power amplifier, while still meeting adjacent channel leakage ratio (ACLR) requirements in the Tx signal chain for compliance
with 3GPP and European Telecommunications Standards Institute (ETSI) standards for 5GNR, LTE and other technologies. The
DPD function in the transceiver supports a carrier bandwidth of up to 200 MHz.
DIGITAL FRONT-END SYSTEM LEVEL OVERVIEW
The transceiver provides digital signal processing capabilities in the embedded ARM processor using closed-loop feedback
signals from the observation receiver channels. These functions improve transmitter performance, measure system output, and
reduce system power consumption. The list of functions includes the following: digital pre-distortion (DPD), closed-loop gain
control (CLGC) and crest factor reduction (CFR). These functions are collectively grouped together as the transceiver digital front
end (DFE).
Figure 1 is a simplified system level overview of the transceiver signal chain with DFE processing blocks highlighted. There are
five main DFE processing blocks:
1.
CFR and hard clipper are used to reduce peak to average power ratio (PAPR) of the baseband signal, especially for multi-
carrier waveforms such as OFDM. With reduced PAPR, the PA can operate at a higher output power, increasing the PA
efficiency. This function is explained in the Crest Factor Reduction (CFR) section.
2.
There are two half band filters with a total interpolation factor of 4x before the DPD actuator. These blocks can provide a
total of 1x, 2x or 4x interpolation.
3.
There are three DPD capture buffers, which include pre-DPD actuator, post-DPD actuator, and observation buffers. Each
buffer can capture a maximum of 4096 samples.
4.
DPD actuator, which applies the inverse PA model to the baseband signal for power amplifier linearization.
5.
Dual core embedded ARM processor in which the DPD and CLGC algorithms reside. One of the dual core ARM processors is a
control processor(ARM-C) which is the master and the second core is a dedicated ARM core for DPD processing (ARM-D).
BBIC
Tx
Upsamp
& LPF
DPD
ACTUATOR
LPF
LPF
DAC
ADC
PFIR
BBIC
Rx
LO
atte
n
Tx analog atten
ORx atten
CFR
PFIR
ORx Obs
Buffer
DPD and CLGC data
capture and
computation
ORx
DDC
(
Optional)
CLGC Loop Gain Ctrl
DFE Signal Processing
Figure 1. ADRV9029 Signal Chain with DFE Processing Blocks Highlighted