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Rev 30 Sep 2013 14:51 | Page 4

FPGA Configuration for ZedBoard

Run the download.bat script from the ”../bin” folder downloaded from the github (see the links in the
download section of the wiki page). The script will automatically configure the ZYNQ SoC and
download the *.elf file afterwards.

If the download script fails to run, modify the Xilinx Tools path in download.bat
to match your Xilinx Installation path.

If programming was successful, you should be seeing messages appear on the terminal window as
shown in figures below. After programming the ADP5589 device, the program will display initialization
messages, and afterwards it will enter Key Decoder Test Mode. In this mode, you can press any key
on the PmodKYPD, and it will be displayed on the UART along with the corresponding event
(press/release). Pressing the [F] key will exit Key Decoder Test Mode. Next the program will Lock the
keypad. Unlocking it requires the combination [1] [A].

Summary of Contents for ADP5589

Page 1: ...exys 3 Spartan 6 FPGA Board Digilent Avnet ZedBoard Quick Start Guide The bit file provided in the project zip file combines the FPGA bit file and the SDK elf files It may be used for a quick check on...

Page 2: ...ADP5589_ board_name zip to the location you desire To begin connect the PmodKYPD to J1 connector of PmodIOXP After that connect the PmodIOXP board to J4 connector of LX9 board pins 3 to 6 see image b...

Page 3: ...on cable for ease of use Connect the USB cables from the PC to the board one for programming Digilent USB device and one for the UART terminal FT232R USB UART FPGA Configuration for Nexys3 and LX 9 Mi...

Page 4: ...to match your Xilinx Installation path If programming was successful you should be seeing messages appear on the terminal window as shown in figures below After programming the ADP5589 device the pro...

Page 5: ...information is displayed on a UART terminal The hardware I2C access allows reading or writing of any ADP5589 registers via the address write and read data registers PmodIOXP must be connected to J4 u...

Page 6: ...E_I2C 1 Timer interrupts used in the design define USE_TIMER 0 External interrupts used in the design define USE_EXTERNAL 0 GPIO used in the design define USE_GPIO 0 Downloads Avnet LX 9 MicroBoard Re...

Page 7: ...FMCOMMS1 EBZ by cherif chibane ll mit edu No Os reference design main function by Jetmiri sample period at vivado hw manager view by woong lee AD9361 REF_CLK by dinc coherentlogix com Analog Devices I...

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