EVAL-ADP5588
Rev. 0 | Page 13 of 20
SCHEMATICS
08102
-02
8
RS
T
b
SC
L
SD
A
Row2
Ro
w
1
Ro
w
0
Co
l0
Co
l1
Co
l2
Co
l3
Col4
VCC
VCC
IN
T
b
VCC
VCC
VCC
RSTb
Col4
Col3
Col2
Col1
SDA
SCL
Row2
Row1
Row0
Col0
INTb
VBoard
Col5
Col6
Col7
Col8_Sens1
Col9_Sens2
Row3
Row4
Row5
Row6
Row7
Col5
Col6
Col7
Col8_Sens1
Col9_Sens2
Row7
Row6
Row5
Row4
Row3
Place LK1, LK2, C19
and C20 as closed to
U2 as possible.
1
2
LK3 1 Way Link
LK3 1 Way Link
C1
1UF/16V
C1
1UF/16V
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
J2
J2
1
2
LK2 1 Way Link
LK2 1 Way Link
1
2
LK1 1 Way Link
LK1 1 Way Link
C19
0.1UF
C19
0.1UF
R7
1
R6
2
R5
3
R4
4
R3
5
R2
6
R1
7
R0
8
C0
9
C1
10
C2
11
C3
12
C4
13
C5
14
C6
15
C7
16
C8
17
C9
18
GN
D
19
RS
T
20
VC
C
21
SD
A
22
SC
L
23
IN
T
24
U1
ADP5588
U1
ADP5588
C20
0.1UF
C20
0.1UF
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
J1
J1
20
Figure 27. Daughterboard Schematic