ADP1974-EVALZ User Guide
UG-883
Rev. 0 | Page 5 of 12
FAULT Test Point
Connect FAULT to VIN or apply an external voltage between 0 V
and 60 V. If SYNC is configured as an output, when V
FAULT
≥ 1.2 V
(typical), a square wave is visible on the SYNC pin operating at
the frequency set by R
FREQ
.
SYNC Test Point
If SYNC is configured as an output, connect an oscilloscope to
SYNC. The SYNC signal is visible when V
EN
≥ 1.25 V (typical)
and V
FAULT
≥ 1.2 V (typical).
If SYNC is configured as an input, connect a signal with f
SW
between 50 kHz and 300 kHz, with V
SYNC(HIGH)
≥ 1.2 V (typical)
and V
SYNC(LOW)
≤ 1.05 V (typical).
COMP Test Point
Connect an external power supply to COMP. See Figure 8 for
the relationship between V
COMP
and the switching duty cycle of
DH and DL.
100
80
60
40
20
0
0.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
DUT
Y
CY
CL
E
(
%)
V
COMP
(V)
13517-
008
T
A
= 25°C
Figure 8. Duty Cycle vs. V
COMP
, R
FREQ
= 100 kΩ, No Load on DL, DH, or DMAX
DL and DH Test Point
Connect the DH and DL pins to an oscilloscope. To observe a
signal on DH or DL, enable the
ADP1974
via the EN pin by
setting V
EN
≥ 1.25 V (typical), V
FAULT
≥ 1.2 V (typical), and
V
COMP
≥ 0.5 V (typical).
If V
MODE
≤ 1.05 V (typical), the
ADP1974
is in boost/recycle
mode, and a square wave is visible on the DL pin. A
complementary square wave is visible on the DH pin.
0.5V
4.5V
2.5V
BOOST MODE CONFIGURATION
MODE ≤ 1.05V (TYPICAL)
V
SCFG
≥ 4.53V (TYPICAL)
COMP
0V
DH
DL
0V
INTERNAL RAMP
(4V p-p)
VREG (5V TYPICAL)
VREG (5V TYPICAL)
0V
13517-
009
Figure 9. Signal Diagram for Boost Configuration
If V
MODE
≥ 1.20 V (typical), the
ADP1974
is in buck/charge
mode, and a square wave is visible on the DH pin. A
complementary square wave is visible on the DL pin.
BUCK MODE CONFIGURATION
MODE ≥ 1.20V (TYPICAL)
V
SCFG
≥ 4.53V (TYPICAL)
13517-
010
0.5V
4.5V
COMP
0V
DH
DL
0V
INTERNAL RAMP
(4V p-p)
VREG (5V TYPICAL)
VREG (5V TYPICAL)
0V
2.5V
Figure 10. Signal Diagram for Buck Configuration
CL Test Point
Unless testing the current limit, connect CL to GND1 or GND2.
If testing the current, see the
ADP1974
data sheet for more infor-
mation about current limits and selecting R
S
to set the current limit.
ADJUSTING THE
ADP1974-EVALZ
COMPONENTS
FOR A SPECIFIC APPLICATION
For more detailed guidance in selecting the components to
customize the features of the
ADP1974
, consult the
ADP1974
data sheet.
Selecting R
FREQ
for a Master Device
When V
SCFG
is ≥ 4.53 V, the
ADP1974
operates as a master device.
When functioning as a master device, the
ADP1974
operates at
the frequency set by the external R
FREQ
resistor connected
between FREQ and ground, and the
ADP1974
outputs a clock
at the programmed frequency on the SYNC pin.
