ADAV4622
Rev. B | Page 23 of 2
8
Synchronous Inputs and Outputs
The synchronous digital inputs and outputs can use any of the
BCLK or LRCLK inputs as a clock and framing signal. By
default, BCLK1 and LRCLK1 are the serial clocks used for the
synchronous inputs. The synchronous port for the ADAV4622
is in slave mode by default, which means the user must supply
the appropriate serial clocks, BCLK and LRCLK. The
synchronous port can also be set to master mode, which means
that the appropriate serial clocks, BCLK and LRCLK, can be
generated internally from the MCLK; therefore, the user does
not need to provide them. The serial data inputs are capable of
accepting all the popular audio transmission standards (see the
Serial Data Interface section for more details).
Asynchronous Inputs
The ADAV4622 has two SRCs, SRC1 and SRC2, that can be
used for converting digital data, which is not synchronous to
the master clock. Each SRC can accept input sample rates in the
range of 5 kHz to 50 kHz. Data that has been converted by the
SRC is inputted to the part and is then synchronous to the
internal audio processor.
The SRC1 is a 2-channel (single-stereo) sample rate converter
that is capable of using any of the three serial clocks available.
The SRC1 can accept data from any of the serial data inputs
(SDIN0, SDIN1, SDIN2, and SDIN3). Once selected as an input
to the SRC, this SDIN line is assumed to contain asynchronous
data and is then masked as an input to the audio processor to
ensure that asynchronous data is not processed as synchronous
data. By default, SRC1 uses the LRCLK0 and BCLK0 as the
clock and framing signals.
The SRC2 is a 6-channel (3-stereo) sample rate converter that is
capable of using any of the three serial clocks available. The
SRC2 can accept data from any of the serial data inputs (SDIN0,
SDIN1, SDIN2, and SDIN3). Once selected as an input to the
SRC, this SDIN line is assumed to contain asynchronous data
and is then masked internally as an input to the audio processor
to ensure that asynchronous data is not processed as
synchronous data. By default, SRC2 uses the LRCLK2 and
BCLK2 as the clock and framing signals.
The first output (SRC2A) from SRC2 is always available to the
audio processor. The other two outputs are muxed with two of
the serial inputs before being available to the audio processor.
SRC2B is muxed with SDIN2 and SRC2C is muxed with SDIN3.
By default, these muxes are configured so that the synchronous
inputs are available to the audio processor. The SRC2B and
SRC2C channels can be made available to the audio processor
simply by enabling them by register write.
When using the ADAV4622 in an asynchronous digital-in-to-
digital-out configuration, the input digital data are input to the
audio processor core from one of the SRCs, using the assigned
BCLK/LRCLK as a framing signal. The digital output is
synchronous to the BCLK/LRCLK, which is assigned to the
synchronous port; the default clocks in this case are BCLK1 and
LRCLK1.
Serial Data Interface
LRCLK is the framing signal for the left- and right-channel
inputs, with a frequency equal to the sampling frequency (f
S
).
BCLK is the bit clock for the digital interface, with a frequency
of 64 × f
S
(32 BCLK periods for each of the left and right
channels).
The serial data interface supports all the popular audio interface
standards, such as I
2
S, left-justified (LJ), and right-justified (RJ).
The interface mode is software selectable, and its default is I
2
S.
The data sample width is also software selectable from 16 bits,
20 bits, or 24 bits. The default is 24 bits.
I
2
S Mode
In I
2
S mode, the data are left-justified, MSB first, with the MSB
placed in the second BCLK period following the transition of
the LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the left-channel data transfer, and a low-to-high
transition on the LRCLK signifies the beginning of the right-
channel data transfer (see Figure 26).
LJ Mode
In LJ mode, the data are left-justified, MSB first, with the MSB
placed in the first BCLK period following the transition of the
LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the right-channel data transfer, and a low-to-high
transition on the LRCLK signifies the beginning of the left-
channel data transfer (see Figure 27).
RJ Mode
In RJ mode, the data are right-justified, LSB last, with the LSB
placed in the last BCLK period preceding the transition of
LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the right-channel data transfer, and a low-to-high
transition on the LRCLK signifies the beginning of the left-
channel data transfer (see Figure 28).
DAC VOLTAGE OUTPUTS
The ADAV4622 has eight DAC outputs, configured as four stereo
auxiliary DAC outputs. However, because the flow is customiza-
ble, this is programmable. The output level is 1 V rms full scale.
AUXOUT2L
AUXOUT2R
DAC
AUXOUT1L
AUXOUT1R
DAC
AUXOUT3L
AUXOUT3R
DAC
AUXOUT4L
AUXOUT4R
DAC
07
06
8-
0
25
Figure 25. DAC Output Section
