Evaluation Board
User Guide
UG-XXX
Rev. A | Page 9 of 14
Once values are set, click
PLL cal enable
to calibrate internal
PLL and allow PLL lock detect.
Note: PLL Cal Enable must be performed always every
time the External Clock frequency and/or multiplier is
changed. Always follow with DAC calibration by clicking
the DAC calibration ICON
.
Enabling
PLL enable
automaticallyactivates
Lock detect
enable.
Default value is enabled (checked box). The indicator
Lock detected
displays green light once the PLL is locked.
Figure 9. PLL lock detection
DBLR enable
allows an additional x2 multiplication to the
reference clock.
ICP
selects the charge pump current output of the PLL in the
reference clock multiplier circuitry. Refer to the PLL charge
pump current table of the AD9915 datasheet for the
corresponding current values (0-7) in the drop-down menu. The
default setting is 3 which is 500uA.
Setting the Parallel Port
The default value of
SYNC CLK invert
is disabled
(unchecked box), which sets the normal SYNC_CLK polarity.
The
SYNC CLK enable
sets the internal SYNC_CLK signal
to appear at the SYNC_CLK pin. Refer to Bit Descriptions for
CFR2 table in AD9915 datasheet for more information. The
Data port mode enable
allows parallel data port modulation in
which the modulated DDS signal control parameter(s) are
supplied directly from the 32-bit parallel data port. Make sure
the profile mode and the sweep mode are disabled to allow
parallel data port mode. The 32-bit port can be accessed
through the external I/O header P101. Refer to
Programming
and Function Pins
Section in
AD9915
datasheet for different
configurations. The
Parallel Port Streaming Disable
default
value is logic 0 (unchecked box). This means the Parallel port
streaming bit is disabled. To enable, change it to logic 1 (check
the box). Enabled parallel port streaming means that the data
port continuously samples from the 32-bit parallel data without
the need of IO_UPDATE. See CFR1[17] in the datasheet for
more information.
Auxiliary and IO Control
Clear Phase Accumulator
holds the DDS phase accumulator
in a reset state as long as this bit (Bit 11) is set.
Auto Clear
Phase Accumulator
sets the DDS phase accumulator to a reset
state when the I/O update pin is set high or when a profile
changes.The default output of AD9915 is sine output. To enable
cosine output of DDS, just uncheck the
Enable sine output
checkbox.
Matched Latency Enabled
allows you to align the application
of the frequency tuning word, the phase offset word, and the
amplitude scale factor at the same time. If this bit is cleared
(default value), then those words arrive at the output in the
order listed in the data sheet.
LSB first
configures the serial I/O port for LSB-first format.
SDIO
configures the serial data I/O pin (SDIO). Refer to
AD9915 data sheet for more information on SDIO settings.
Setting Power-Down Controls
These power-down controls allows you to power down each of
the specific circuit blocks individually.
External Power Down Mode
allows you to control which
power-down mode is used in conjunction with the External
Power Down Pin button. The
Fast Recovery
mode maintains
power to the DAC bias circuitry, PLL, VCO and input clock
circuitry. This mode uses significantly more power than the
Power Down
mode but allows the device to be awaken very
quickly from power-down state. The
Power Down
mode stops
clocks and powers down bias circuits. This mode takes
significantly longer to power back up from a power-down state.
See the Power-Down Control section in AD9915 data sheet for
more information. Checked
Clock input power down
box will
disable REFCLK input circuits and PLL. Default value is
enabled (unchecked box).
DAC power-down
default value
(unchecked box) sets the DAC clock signals and bias circuits
active. To disable, check the checkbox.
Digital power down
default value sets the digital core active. To disable, just change
logic to 1 (check the box).
OSK
To select the OSK function of the AD9915, select the
OSK
Enable
check box.
External OSK enable
allows you to use
manual (default) or automatic OSK function. Refer to AD9915
data sheet for more information on these bits on CFR1. Use of
External OSK pin activate
functionality depends on the state
of the external OSK control bit and OSK enable bit. Refer to
Figure 31.OSK Block Diagram of AD9915 data sheet for more
information.
Clock Calibration
Checking the
DAC calibration
checkbox has the same
function with the
DAC calibration ICON
.
Auxiliary divider is an internal divider in AD9915that is used
as a part of clock calibration process. The default value is
enabled. Once the
Auxiliary divider power down
is checked,
the auxiliary divider is powered down, thus disabling clock
calibration.
The default value of
Cal clock power down
is unchecked. It
means that the clock calibration is enabled. To disable internal
clock calibration, activate the power down function by
checking the checkbox.
