Analog Devices AD9843A User Manual Download Page 2

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AD9843A–SPECIFICATIONS

GENERAL SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

TEMPERATURE RANGE

Operating

–20

+85

°

C

Storage

–65

+150

°

C

POWER SUPPLY VOLTAGE

Analog, Digital, Digital Driver

2.7

3.6

V

POWER CONSUMPTION

Normal Operation

(Specified Under Each Mode of Operation)

Power-Down Modes

Fast Recovery Mode

45

mW

Standby

5

mW

Total Power-Down

1

mW

MAXIMUM CLOCK RATE

20

MHz

A/D CONVERTER

Resolution

10

Bits

Differential Nonlinearity (DNL)

±

0.4

±

1.0

LSB

No Missing Codes

10

Bits Guaranteed

Full-Scale Input Voltage

2.0

V

Data Output Coding

              Straight Binary

VOLTAGE REFERENCE

Reference Top Voltage (VRT)

2.0

V

Reference Bottom Voltage (VRB)

1.0

V

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Unit

LOGIC INPUTS

High Level Input Voltage

V

IH

2.1

V

Low Level Input Voltage

V

IL

0.6

V

High Level Input Current

I

IH

10

µ

A

Low Level Input Current

I

IL

10

µ

A

Input Capacitance

C

IN

10

pF

LOGIC OUTPUTS

High Level Output Voltage, I

OH

 = 2 mA

V

OH

2.2

V

Low Level Output Voltage, I

OL

 = 2 mA

V

OL

0.5

V

Specifications subject to change without notice.

(T

MIN

 to T

MAX

, AVDD = DVDD = 3.0 V, f

DATACLK

 = 20 MHz, unless otherwise noted.)

(DRVDD = 2.7 V, C

L

 = 20 pF unless otherwise noted.)

Summary of Contents for AD9843A

Page 1: ...with 6 Bit Resolution 2 dB to 36 dB 10 Bit Variable Gain Amplifier VGA Low Noise Clamp Circuits Analog Preblanking Function 10 Bit 20 MSPS A D Converter Auxiliary Inputs with VGA and Input Clamp 3 Wir...

Page 2: ...cale Input Voltage 2 0 V Data Output Coding Straight Binary VOLTAGE REFERENCE Reference Top Voltage VRT 2 0 V Reference Bottom Voltage VRB 1 0 V Specifications subject to change without notice DIGITAL...

Page 3: ...2 dB See Page 13 for Gain Equations Max Gain VGA Code 1023 36 dB BLACK LEVEL CLAMP Clamp Level Resolution 256 Steps Clamp Level Measured at ADC Output Min Clamp Level 0 LSB Max Clamp Level 63 75 LSB...

Page 4: ...ODE SPECIFICATIONS Parameter Min Typ Max Unit POWER CONSUMPTION 60 mW MAXIMUM CLOCK RATE 20 MHz INPUT BUFFER Same as AUX1 MODE VGA Max Output Range 2 0 V p p Gain Control Resolution 512 Steps Gain Sel...

Page 5: ...UTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD98...

Page 6: ...s Reference Level 22 SHD DI CDS Sampling Clock for CCD s Data Level 23 CLPDM DI Input Clamp Clock Input 25 26 35 AVSS P Analog Ground 27 AVDD1 P Analog Supply 28 BYP1 AO Internal Bias Level Decoupling...

Page 7: ...calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting The output noise can be converted to an equivalent voltage using the relationship 1 LSB AD...

Page 8: ...60 80 90 15 VDD 3 3V VDD 3 0V VDD 2 7V TPC 1 Power vs Sample Rate 0 1000 400 200 600 800 0 0 5 0 5 0 25 0 25 TPC 2 Typical DNL Performance Typical Performance Characteristics VGA GAIN CODE LSB 4 2 0 0...

Page 9: ...IVE PIXELS CLPOB CLPDM OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS PBLK NOTES 1 CLPOB AND CLPDM WILL OVERWRITE PBLK PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM...

Page 10: ...OCCURS ON SL RISING EDGE Figure 8 Serial Write Operation SDATA SCK SL RNW TEST 1 0 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 tDS tDH tLS tLH NOTES 1 RNW READ NOT WRITE SET HIGH FOR READ OPERATION 2 TES...

Page 11: ...nts Default Value x080 MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clamp Level LSB X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 25 0 0 0 0 0 0 1 0 0 5 1 1 1 1 1 1 1 0 63 5 1 1 1 1 1 1 1 1 63 75 Table V Con...

Page 12: ...ee Tables V and VI for more details A CDS gain of 4 dB provides some front end signal gain and improves the overall signal to noise ratio This gain setting works very well in most applications and the...

Page 13: ...Interface Timing and Inter nal Register Description section When the loop is disabled the Clamp Level Register may still be used to provide pro grammable offset adjustment Horizontal timing is shown i...

Page 14: ...NAL V 0 8V 0 4V MIDSCALE 0dB TO 36dB Figure 14 AUX1 Circuit Configuration 0dB TO 18dB 8 AUX2IN BUFFER 0 1 F VIDEO SIGNAL 9 CLAMP LEVEL LPF VGA GAIN REGISTER ADC VGA VIDEO CLAMP CIRCUIT CLAMP LEVEL REG...

Page 15: ...ins 25 through 39 This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins All decoupling ca...

Page 16: ...inches and mm 48 Lead LQFP ST 48 TOP VIEW PINS DOWN 1 12 13 25 24 36 37 48 0 019 0 5 BSC 0 276 7 00 BSC SQ 0 011 0 27 0 006 0 17 0 354 9 00 BSC SQ 0 063 1 60 MAX 0 030 0 75 0 018 0 45 0 008 0 2 0 004...

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