Evaluation Board for AD9510
AD9510/PCB
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Full-featured evaluation board for the AD9510
PC evaluation software for control and exercise
of the AD9510
USB interface
APPLICATIONS
AD9510 performance evaluation
GUI control panel for learning AD9510 programming
EVALUATION BOARD DESCRIPTION
This user guide describes the AD9510 evaluation board
hardware and software. The software provides a graphical
user interface (GUI) for easy interface with the various on-
chip functions of the AD9510. This allows for a thorough
exploration and evaluation of the AD9510’s operation,
performance, and capabilities.
Note that the AD9510
evaluation board software should be installed before
connecting the AD9510 evaluation board to the PC.
The AD9510 is a highly sophisticated, performance clock
distribution part with numerous user programmable functions.
To use the evaluation board properly, see the current data sheet
for the AD9510 on the Analog Devices website. You can
download the data sheet from www.analog.com/AD9510.
Note that this user guide includes instructions for both the
AD9510/PCB and AD9510-VCO/PCB, which includes a
245.76 MHz VCXO and loop filter.
AD9510 DEVICE DESCRIPTION
The AD9510 provides a multi-output clock distribution
function along with an on-chip phase-locked loop (PLL)
core. The design emphasizes low jitter and phase noise to
maximize data converter performance. Other applications
with demanding phase noise and jitter requirements also
benefit from this part.
The PLL section consists of a programmable reference divider
(R), a low noise phase frequency detector (PFD), a precision
charge pump (CP), and a programmable feedback divider (N).
By connecting an external VCXO or VCO to the CLK2/CLK2B
pins, frequencies up to 1.6 GHz may be synchronized to the
input reference.
There are eight independent clock outputs: four are LVPECL
(1.2 GHz), and four are selectable as either LVDS (800 MHz) or
CMOS (250 MHz).
Each output has a programmable divider can be bypassed or set
to divide by any integer up to 32. The phase of one clock output
relative to another clock output can be varied by means of a
divider phase select function that serves as a coarse timing
adjustment. Two of the LVDS/CMOS outputs feature program-
mable delay elements with full-scale ranges up to 10 ns of delay.
This fine tuning delay block has 5-bit resolution, giving 32
possible delays from which to choose for each full-scale setting.
05632-
001
Figure 1. AD9510 Evaluation Board
