Analog Devices AD9273, Manual

Page: 36 / 49

AD9273
Rev. B | Page 35 of 48
600
–400
400
–200
200
–600
0
–1.5ns –0.5ns –1.0ns 0ns 0.5ns 1.0ns 1.5ns
E
Y
E
DI
AG
RAM
V
O
L
T
AG
E
(
V
)
EYE: ALL BITS
ULS: 2396/2396
25
0
5
10
15
20
–200ps –100ps 0ps 100ps 200ps
T
IE J
IT
T
ER
H
IST
O
G
R
A
M
(H
it
s
)
0
70
30
-03
7
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 11.
To change the output data format to twos complement, see the
Memory Map section.
Table 11. Digital Output Coding
Code
(VIN+) − (VIN−),
Input Span = 2 V p-p (V) Digital Output Offset Binary
(D11 ... D0)
4095 +1.00 1111 1111 1111
2048 0.00 1000 0000 0000
2047 −0.000488 0111 1111 1111
0 −1.00 0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 600 Mbps
(12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See Table 17 for details on enabling this
feature.
Two output clocks are provided to assist in capturing data from
the AD9273. DCO± is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9273 and must be captured on the rising and falling edges of
the DCO± that supports double data rate (DDR) capturing. The
frame clock output (FCO±) is used to signal the start of a new
output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
Figure 67. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination
Resistor and Trace Lengths of Greater than 24 Inches on Standard FR-4
Table 12. Flexible Output Test Modes
Output Test Mode
Bit Sequence
Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to Data
Format Select
0000 Off (default) N/A N/A N/A
0001 Midscale short 1000 0000 0000 1000 0000 0000 Yes
0010 +Full-scale short 1111 1111 1111 1111 1111 1111 Yes
0011 −Full-scale short 0000 0000 0000 0000 0000 0000 Yes
0100 Checkerboard output 1010 1010 1010 0101 0101 0101 No
0101 PN sequence long N/A N/A Yes
0110 PN sequence short N/A N/A Yes
0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No
1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No
1001 1-/0-bit toggle 1010 1010 1010 N/A No
1010 1× sync 0000 0011 1111 N/A No
1011 One bit high 1000 0000 0000 N/A No
1100 Mixed bit frequency 1010 0011 0011 N/A No