Rev 07 Aug 2013 10:33 | Page 9
VCO Divider.
2. Set PLL Charge Pump Current and PLL Loop BW settings to 7.
3. Set the PLL Mode to Manual.
4. Turn on PLL Enable.
5. Set the PLL Mode to Auto.
Figure 9 AD9142A SPI PLL Tab
EVB Jumper Configurations
This evaluation board allows evaluation of both the DAC IF outputs as well as the modulator RF
outputs. By default, the solder jumpers are configured to look at the modulator RF outputs. Below is a
table listing the jumper configurations and SMA connector connections needed to view either output
on a spectrum analyzer.
Output Viewed
SMA Connector
Jumper Configurations
I DAC Output
J3(“DAC1 Output”)
JP4 & JP5 Pins 1-2 (outer pads)
Q DAC Output
J4(“DAC2 Output”)
JP6 & JP7 Pins 1-2 (outer pads)
ADL5372 RF Output
J6(“MOD_OUT”)
JP4, JP5, JP6, JP7 Pins 2-3 (inner pads)
Note: When viewing the modulator output, a local oscillator (LO) must be connected to J15 (”LO_IN”)
to properly modulate the signals
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Summary of Contents for AD9142A-M5372-EBZ
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