Analog Devices AD6659, User Manual

Page: 11 / 40

Evaluation Board User Guide UG-003
Rev. A | Page 11 of 40
Troubleshooting Tips
If the FFT plot appears abnormal, do the following:
•
If you see a normal noise floor when you disconnect the
signal generator from the analog input, be sure you are not
overdriving the ADC. Reduce the input level, if necessary.
•
In VisualAnalog , click the Settings button in the Input
Formatter block. Check that Number Format is set to the
correct encoding (offset binary by default). Repeat for the
other channel.
If the FFT appears normal but the performance is poor, check
the following:
•
Make sure an appropriate filter is used on the analog input.
•
Make sure the signal generators for the clock and the analog
input are clean (low phase noise).
•
Change the analog input frequency slightly if noncoherent
sampling is being used.
•
Make sure the SPI config file matches the product being
evaluated.
If the FFT window remains blank after Run is clicked, do the
following:
•
Make sure the evaluation board is securely connected to
the HSC-ADC-EVALCZ board.
•
Make sure the FPGA has been programmed by verifying
that the
DONE LED is illuminated on the HSC-ADC-
EVALCZ board. If this LED is not illuminated, make sure
the U4 switch on the board is in the correct position for
USB CONFIG.
•
Make sure the correct FPGA program was installed by
selecting the
Settings button in the ADC Data Capture
block in VisualAnalog . Then select the FPGA tab and
verify that the proper FPGA bin file is selected for the part.
If VisualAnalog indicates that the FIFO Capture timed out ,
do the following:
•
Make sure all power and USB connections are secure.
•
Probe the DCOA signal at RN801 (Pin 2) on the evaluation
board and confirm that a clock signal is present at the
ADC sampling rate.