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EVAL-AD5317RDBZ User Guide

UG-970

Rev. A | Page 9 of 13

14449-

012

Figure 12.

EVAL-MBnanoDAC-SDZ

Motherboard Component Placement

14449-

013

Figure 13.

EVAL-MBnanoDAC-SDZ

Motherboard Top Side Routing

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Summary of Contents for AD5317R

Page 1: ...AL SDP CB1Z SDP B board must be purchased separately DOCUMENTS NEEDED Electronic version of the AD5317R data sheet Electronic version of the EVAL AD5317RDBZ user guide GENERAL DESCRIPTION This user guide details the operation of the evaluation board for the AD5317R quad channel voltage output digital to analog converter DAC The evaluation board is designed to help users quickly prototype new AD531...

Page 2: ... 3 Motherboard Power Supplies 3 Motherboard Link Options 3 Daughter Board Link Options 3 Evaluation Board Software Quick Start Procedures 4 Installing the Software 4 Running the Software 4 Software Operation 5 Evaluation Board Schematics and Artwork 7 EVAL MBnanoDAC SDZ Motherboard 7 EVAL AD5317RDBZ Daughter Board 10 Ordering Information 12 Bill of Materials 12 REVISION HISTORY 8 2017 Rev 0 to Rev...

Page 3: ...e 3 The positions listed in Table 2 and Table 3 match the evaluation board imprints see Figure 12 Table 2 Link Options Setup for SDP B Control Default Link No Position REF1 2 5V REF2 EXT REF3 EXT REF4 EXT LK5 C LK6 3 3V LK7 B DAUGHTER BOARD LINK OPTIONS The printed circuit board PCB for this board is shared between the EVAL AD5316RDBZ and EVAL AD5317RDBZ daughter boards To configure for the EVAL A...

Page 4: ...cluded in the evaluation kit 5 When the software detects the evaluation board click through any dialog boxes that appear to finalize the installation RUNNING THE SOFTWARE To run the program take the following steps 1 Connect the evaluation board to the SDP B board and connect the USB cable between the SDP B board and the PC 2 Power up the evaluation board as described in the Motherboard Power Supp...

Page 5: ...ected DAC The DAC outputs are automatically updated with the appropriate voltage The LDAC MASK setting is ignored LDAC Control Click Pulse LDAC to bring the LDAC pin low and then back high Doing this copies the data from the input registers to the DAC registers and the outputs update accordingly Any DAC updates disabled by the LDAC MASK settings are ignored Alternatively the LDAC pin can be set to...

Page 6: ...l scale output of 5 V 14449 006 Figure 6 Gain Control Window LDAC Mask Register Each DAC can be configured to respond to or ignore the LDAC pin settings in the LDAC Configuration window Click the blue progressive disclosure option to access the LDAC Configuration window as shown in Figure 7 When the LDAC selections are completed click OK to write the appropriate values to the AD5317R The LDAC MASK...

Page 7: ...ND 45 GPIO4 44 GPIO2 43 GPIO0 42 SCL_1 41 SDA_1 40 GND 39 SPI_SEL1 SPI_SS 38 SPI_SEL_C 37 SPI_SEL_B 36 GND 35 SPORT_INT 34 SPI_D3 33 SPI_D2 32 SPORT_DT1 31 SPORT_DR1 30 SPORT1_TDV 29 SPORT0_TDV 28 GND 27 PAR_FS1 26 PAR_FS3 25 PAR_A1 24 PAR_A3 23 GND 22 PAR_CS 21 PAR_RD 20 PAR_D1 19 PAR_D3 18 PAR_D5 17 GND 16 PAR_D7 15 PAR_D9 14 PAR_D11 13 PAR_D13 12 PAR_D14 11 GND 10 PAR_D17 9 PAR_D19 8 PAR_D21 7 ...

Page 8: ...R PD GAIN SDA 1 2 3 4 5 6 7 8 J9 J8 1 J8 2 J8 3 J8 4 J8 5 J8 6 J7 1 J7 2 J7 3 J7 4 J7 5 J7 6 J3 1 J3 2 J3 3 J3 4 J3 5 J3 6 J4 1 J4 2 J4 3 J4 4 J4 5 J4 6 J4 7 J4 8 VDD VREF1 VREF2 VREF3 VREF4 VLOGIC SDA SCL SYNC SCLK SDO SDIN LDAC CLR PD GAIN DB6 DB7 DB8 DB9 DB0 DB1 DB2 DB3 VOUT_0 VOUT_1 VOUT_2 VOUT_3 VOUT_4 VOUT_5 VOUT_6 VOUT_7 SCL SDA DGND VLOGIC SCL SDA DGND VLOGIC SYNC SDO SDIN SCLK DGND VLOGIC...

Page 9: ...EVAL AD5317RDBZ User Guide UG 970 Rev A Page 9 of 13 14449 012 Figure 12 EVAL MBnanoDAC SDZ Motherboard Component Placement 14449 013 Figure 13 EVAL MBnanoDAC SDZ Motherboard Top Side Routing ...

Page 10: ...NP C7 DNP C8 DNP A B LK2 A B LK1 1 3 5 7 9 2 4 6 8 10 J2 J3 1 J3 2 J3 3 J3 4 J3 5 J3 6 J4 1 J4 2 J4 3 J4 4 J4 5 J4 6 J4 7 J4 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J1 R5 DNI R6 DNI R9 DNI R10 DNI R12 DNI R13 DNI R7 0Ω R8 0Ω R11 0Ω GAIN LDAC PD VDD VLOGIC VREF1 VOUT_0 VOUT_1 VOUT_2 VOUT_3 SDA SCL SYNC SCLK SDIN VLOGIC VDD VDD VREF1 VREF2 VREF3 VREF4 VLOGIC SDA SCL SYNC SCLK SDO SDIN LDAC CLR PD G...

Page 11: ...70 Rev A Page 11 of 13 14449 016 Figure 16 EVAL AD5317RDBZ Daughter Board Component Placement 14449 017 Figure 17 EVAL AD5317RDBZ Daughter Board Top Side Routing 14449 018 Figure 18 EVAL AD5317RDBZ Daughter Board Bottom Side Routing ...

Page 12: ...4 1 U2 3 3 V linear regulator Analog Devices ADP121 AUJZ33R7 1 U3 32 kb I2 C serial EEPROM FEC 1331330 1 U4 5 V reference MSOP Analog Devices ADR445ARMZ 1 U5 Ultralow noise XFET voltage reference Analog Devices ADR431BRZ 1 U6 4 096 V reference Analog Devices REF198ESZ 1 U7 Dual op amp Analog Devices AD8616ARZ 1 U10 Quad op amp Analog Devices AD8608ARMZ 2 U11 U12 Op amp Analog Devices AD8655ARMZ 1 ...

Page 13: ...ransfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modi...

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